ATMEGA32L-8AU Atmel, ATMEGA32L-8AU Datasheet - Page 232

• Manufacturer Part Number: ATMEGA32L-8AU
• Description: IC AVR MCU 32K 8MHZ 3V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.7-5.5 V
• Data Rom Size: 1024 B
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10 mm
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Scanning the Analog
Comparator
2503Q–AVR–02/11
Figure 120. Boundary-scan Cells for Oscillators and Clock Options
Table 89
XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Table 89. Scan Signals for the Oscillators
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Enable Signal
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
TOSKON
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
Previous
From
Cell
summaries the scan registers for the external clock pin XTAL1, Oscillators with
the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided. The INTCAP fuses are not supported
in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring inter-
nal capacitors to run unless the fuse is correctly programmed.
ShiftDR
Table
0
1
ClockDR
RCCK
TOSCK
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
90.
D
UpdateDR
Q
Next
Cell
To
Figure 122
D
G
Q
EXTEST
0
1
is attached to each of these signals. The signals are
Clock Option
External Clock
External Crystal
External Ceramic
Resonator
External RC
Low Freq. External Crystal
32kHz Timer Oscillator
XTAL1/TOSC1
(1)(2)(3)
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
Previous
Scanned Clock Line
when not Used
From
Cell
ATmega32(L)
ShiftDR
0
1
ClockDR
0
0
1
0
0
D
Figure
FF1
Q
Next
Cell
To
121. The
232