ATMEGA32L-8AU Atmel, ATMEGA32L-8AU Datasheet
ATMEGA32L-8AU
Specifications of ATMEGA32L-8AU
Available stocks
Related parts for ATMEGA32L-8AU
ATMEGA32L-8AU Summary of contents
Page 1
... I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V for ATmega32L – 4.5V - 5.5V for ATmega32 • Speed Grades – 8MHz for ATmega32L – 16MHz for ATmega32 • ...
Page 2
Pin Configurations Figure 1. Pinout ATmega32 2503Q–AVR–02/11 PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) ...
Page 3
... Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram VCC GND AVCC AREF 2503Q–AVR–02/11 ® ...
Page 4
... Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effec- tive solution to many embedded control applications. The Atmel AVR ATmega32 is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits. ...
Page 5
Port B (PB7..PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins ...
Page 6
... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...
Page 7
About Code This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before Examples compilation. Be aware that not all C ...
Page 8
... AVR CPU Core Introduction This section discusses the Atmel CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Figure 3. Block Diagram of the AVR MCU Architecture Overview In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data ...
Page 9
... Space locations following those of the Register File, $20 - $5F. ALU Arithmetic – The high-performance Atmel purpose working registers. Within a single clock cycle, arithmetic operations between general Logic Unit purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementa- tions of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “ ...
Page 10
Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated ...
Page 11
... The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose The Register File is optimized for the Atmel achieve the required performance and flexibility, the following input/output schemes are sup- Register File ported by the Register File: • ...
Page 12
The X-register, Y- The registers R26..R31 have some added functions to their general purpose usage. These reg- register and Z-register isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and ...
Page 13
... Figure 7. Single Cycle ALU Operation Register Operands Fetch ALU Operation Execute Reset and The Atmel reset vector each have a separate program vector in the program memory space. All interrupts Interrupt Handling are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt ...
Page 14
The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to information. The Reset Vector can also be moved to the start ...
Page 15
... Interrupt Response The interrupt execution response for all the enabled Atmel Time minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack ...
Page 16
... ATmega32 This section describes the different memories in the Atmel ture has two main memory spaces, the Data Memory and the Program Memory space. In Memories addition, the ATmega32 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
Page 17
... SRAM in the ATmega32 are all accessible through all these addressing modes. The Register File is described in Figure 9. Data Memory Map 2503Q–AVR–02/11 ® ® shows how the Atmel AVR ATmega32 SRAM Memory is organized. “General Purpose Register File” on page Register File R0 ...
Page 18
Data Memory Access This section describes the general access timing concepts for internal memory access. The Times internal data SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATmega32 contains 1024 bytes ...
Page 19
The EEPROM Address Register – EEARH and Bit EEARL Read/Write Initial Value • Bits 15..10 – Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. • Bits 9..0 – EEAR9..0: EEPROM Address The ...
Page 20
Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the ...
Page 21
Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned ...
Page 22
The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
Page 23
EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level ...
Page 24
System Clock and Clock Options Clock Systems Figure 11 need not be active at a given time. In order to reduce power consumption, the clocks to modules and their not being used can be halted by using different sleep modes, ...
Page 25
ADC Clock – clk The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks ADC in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources ...
Page 26
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. The CKOPT Fuse selects between two different ...
Page 27
The CKSEL0 Fuse together with the SUT1..0 fuses select the start-up times as shown in 5. Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 Notes: 2503Q–AVR–02/11 Start-up Time from ...
Page 28
Low-frequency To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Crystal Oscillator Oscillator must be selected by setting the CKSEL fuses to “1001”. The crystal should be con- nected as shown in ...
Page 29
... RC Oscillator. At 5V, 25°C and 1.0MHz Oscillator frequency selected, this calibration gives a frequency within ±3% of the nominal frequency. Using calibra- tion methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±1% accuracy at any given V Chip Clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the reset time-out. For more information on the pre-programmed calibration value, see the section bration Byte” ...
Page 30
When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 10. XTAL1 and XTAL2 should be left unconnected (NC). Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection SUT1..0 00 ...
Page 31
External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 14. To run the device on an external clock, the CKSEL fuses must be programmed to “0000”. By programming the CKOPT Fuse, ...
Page 32
Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...
Page 33
Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue ...
Page 34
Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. ...
Page 35
Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if ...
Page 36
System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute ...
Page 37
... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega32L and BODLEVEL = 0 for ATmega32. BODLEVEL = 1 is not applicable for ATmega32. ATmega32(L) DATA BUS ...
Page 38
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. ...
Page 39
External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset ...
Page 40
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 41 Figure 20. Watchdog ...
Page 41
Internal Voltage ATmega32 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated ...
Page 42
Watchdog Timer Control Register – Bit WDTCR Read/Write Initial Value • Bits [7:5] – Reserved Bits These bits are reserved bits in the ATmega32 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit ...
Page 43
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. ...
Page 44
Interrupts This section describes the specifics of the interrupt handling as performed in ATmega32. For a general explanation of the AVR interrupt handling, refer to page 13. Interrupt Vectors in ATmega32 Table 18. Reset and Interrupt Vectors Vector No. 1 ...
Page 45
Table 19. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega32 is: Address $000 $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 ...
Page 46
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4 Kbytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
Page 47
Moving Interrupts The General Interrupt Control Register controls the placement of the Interrupt Vector table. Between Application and Boot Space General Interrupt Control Register – Bit GICR Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the ...
Page 48
Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
Page 49
I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
Page 50
Ports as General The ports are bi-directional I/O ports with optional internal pull-ups. Digital I/O description of one I/O-port pin, here generically called Pxn. Figure 23. General Digital I/O Note: Configuring the Pin Each port pin consists of three register ...
Page 51
If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user ...
Page 52
When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in clock. In this case, the delay t Figure 25. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK INSTRUCTIONS SYNC LATCH ...
Page 53
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
Page 54
Unconnected pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should ...
Page 55
Table 21 ure 26 the modules having the alternate function. Table 21. Generic Description of Overriding Signals for Alternate Functions Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions ...
Page 56
Special Function I/O Register – SFIOR Bit Read/Write Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
Page 57
Table 24. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Alternate Functions of The Port B pins with alternate functions are shown in Port B Table 25. Port B ...
Page 58
MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the ...
Page 59
Table 26. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 27. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV ...
Page 60
Alternate Functions of The Port C pins with alternate functions are shown in Port C the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. Table 28. Port C Pins Alternate Functions Port ...
Page 61
SDA – Port C, Bit 1 SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data I/O ...
Page 62
Table 30. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Alternate Functions of The Port D pins with alternate functions are shown in Port D Table 31. Port ...
Page 63
OC1A – Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) ...
Page 64
Table 33. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Register Description for I/O Ports Port A Data Register – PORTA Bit Read/Write Initial Value Port A Data Direction ...
Page 65
Port B Input Pins Address – PINB Bit Read/Write Initial Value Port C Data Register – PORTC Bit Read/Write Initial Value Port C Data Direction Register – DDRC Bit Read/Write Initial Value Port C Input Pins Address – PINC Bit ...
Page 66
External The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides Interrupts a way of generating a software ...
Page 67
Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre- sponding interrupt mask are set. The ...
Page 68
INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 ...
Page 69
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: Timer/Counter0 • Single Compare Unit Counter with PWM • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) ...
Page 70
Unit” on page 71. which can be used to generate an output compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case ...
Page 71
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0). There are close connections between how the counter behaves (counts) and how waveforms are generated ...
Page 72
The OCR0 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled the CPU will access the OCR0 directly. ...
Page 73
Figure 30. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0) from the Waveform Generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output) is ...
Page 74
TCNT0 becomes zero. The bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the There are no special cases to consider in the normal mode, ...
Page 75
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01 provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its sin- gle-slope operation. The counter counts ...
Page 76
MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.) Phase Correct PWM The ...
Page 77
OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated ...
Page 78
Figure 35. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 36 Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 37 2503Q–AVR–02/11 I/O Tn /8) I/O MAX ...
Page 79
Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) OCRn OCFn 2503Q–AVR–02/11 /8) I/O Tn /8) I/O TOP - 1 ATmega32(L) TOP BOTTOM TOP BOTTOM + 1 79 ...
Page 80
Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Bit Read/Write Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with ...
Page 81
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. normal or CTC mode (non-PWM). Table 39. Compare Output Mode, non-PWM Mode COM01 Table 40 mode. Table ...
Page 82
Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 42. Clock Select Bit Description CS02 external pin ...
Page 83
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an ...
Page 84
Timer/Counter0 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and and Timer/Counter0. Timer/Counter1 Prescalers Internal Clock Source The Timer/Counter can be clocked directly by the ...
Page 85
However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) ...
Page 86
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: Timer/Counter1 • True 16-bit Design (that is, allows 16-bit PWM) • Two Independent Output Compare Units • Double ...
Page 87
Figure 40. 16-bit Timer/Counter Block Diagram Note: Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described ...
Page 88
The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture Pin (ICP1 the Analog Comparator pins “Analog Comparator” on page Canceler) for reducing the chance of ...
Page 89
Accessing 16-bit The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via Registers the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer ...
Page 90
The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned ...
Page 91
The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...
Page 92
Figure 41. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk T 1 TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con- taining the upper eight bits of the ...
Page 93
Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ICP1 ...
Page 94
For more information on how to access the 16-bit registers refer to on page Input Capture Pin The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Source Timer/Counter1 can alternatively use the Analog Comparator ...
Page 95
Waveform Generator for handling the special cases of the extreme values in some modes of operation A special feature of output compare unit A allows it to define the Timer/Counter TOP value (that is, counter resolution). ...
Page 96
For more information of how to access the 16-bit registers refer to on page Force Output In non-PWM Waveform Generation modes, the match output of the comparator can be forced by Compare writing a one to the Force Output Compare ...
Page 97
Figure 44. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out- put) ...
Page 98
Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit ...
Page 99
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output ...
Page 100
Figure 46. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as ...
Page 101
The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM ...
Page 102
Figure 47. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ...
Page 103
The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x ...
Page 104
Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). ...
Page 105
TOP the output will be set to high for non- inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define ...
Page 106
TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 51. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) ...
Page 107
Timer/Counter Register Description Timer/Counter1 Control Register A – Bit TCCR1A Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Compare unit A • Bit 5:4 – COM1B1:0: Compare Output Mode for Compare unit B The COM1A1:0 ...
Page 108
Table 45. Compare Output Mode, Fast PWM COM1A1/COM1B1 Note: Table 46 rect or the phase and frequency correct, PWM mode. Table 46. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COM1A1/COM1B1 Note: • Bit 3 – FOC1A: ...
Page 109
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 1:0 – WGM11:0: Waveform ...
Page 110
Timer/Counter1 Control Register B – Bit TCCR1B Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the ...
Page 111
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Timer/Counter1 – TCNT1H and TCNT1L ...
Page 112
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. ...
Page 113
Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP value, ...
Page 114
Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: Timer/Counter2 • Single Compare unit Counter with PWM and • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator ...
Page 115
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare ...
Page 116
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped. ...
Page 117
The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering ...
Page 118
Figure 56. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is ...
Page 119
Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit ...
Page 120
The waveform generated will have a maximum frequency of f when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, ...
Page 121
OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the coun- ter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N ...
Page 122
Figure 59. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag ( Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation ...
Page 123
Timer/Counter The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk Timing Diagrams is therefore shown as a clock enable signal. In Asynchronous mode, clk the Timer/Counter Oscillator clock. The figures include information on when Interrupt ...
Page 124
Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk clk (clk TCNTn OCRn OCFn Figure 63 Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O (clk TCNTn (CTC) OCRn OCFn ...
Page 125
Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Bit Read/Write Initial Value • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur- ing compatibility ...
Page 126
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. normal or CTC mode (non-PWM). Table 51. Compare Output Mode, non-PWM Mode COM21 Table 52 mode. Table ...
Page 127
Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 54. Table 54. Clock Select Bit Description CS22 Timer/Counter ...
Page 128
Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Bit Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clk written to one, Timer/Counter2 ...
Page 129
The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator ...
Page 130
Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. • During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer ...
Page 131
Timer/Counter Figure 64. Prescaler for Timer/Counter2 Prescaler The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins ...
Page 132
Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32 and peripheral devices or between several AVR devices. The ATmega32 SPI Peripheral includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • ...
Page 133
SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI ...
Page 134
The following code examples show how to initialize the SPI as a master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...
Page 135
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2503Q–AVR–02/11 (1) ; ...
Page 136
SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...
Page 137
Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, ...
Page 138
SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global ...
Page 139
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 67 and ensuring sufficient time for data ...
Page 140
USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or ...
Page 141
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for ...
Page 142
Figure 70. Clock Generation Logic, Block Diagram DDR_XCK Signal description: txclk rxclk xcki xcko fosc Internal Clock Internal clock generation is used for the asynchronous and the synchronous master modes of Generation – The operation. The description in this section ...
Page 143
Table 60. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal Mode (U2X = 0) Asynchronous Double Speed Mode (U2X = 1) Synchronous Master Mode Note: BAUD Baud rate (in bits per second, bps) f OSC UBRR Contents ...
Page 144
Figure 71. Synchronous Mode XCK Timing. The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As ing XCK edge and sampled at falling XCK edge. If UCPOL is ...
Page 145
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by ...
Page 146
USART The USART has to be initialized before any communication can take place. The initialization pro- Initialization cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For ...
Page 147
Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB – The USART Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by the USART ...
Page 148
Sending Frames with If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB 9 Data Bit before the low byte of the character is written to UDR. The following code ...
Page 149
The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is automatically ...
Page 150
Data Reception – The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Regis- The USART ter to one. When the receiver is enabled, the normal pin operation of the RxD pin is overridden by ...
Page 151
Receiving Frames with If 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB 9 Databits before reading the low bits from the UDR. This rule applies to the FE, DOR and ...
Page 152
The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early ...
Page 153
Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXEN is set to zero) the Receiver will no longer override the ...
Page 154
If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts looking for ...
Page 155
Asynchronous The operational range of the receiver is dependent on the mismatch between the received bit Operational Range rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or ...
Page 156
Table 62. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X=1) # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the receiver and transmitter equally divides the maximum ...
Page 157
Multi-processor Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering Communication function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. ...
Page 158
Accessing The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some UBRRH/ UCSRC special consideration must be taken when accessing this I/O location. Registers Write Access When doing a write access of this I/O location, the ...
Page 159
Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. How- ever, in most applications rarely necessary to read any of these registers. The read access is controlled by a ...
Page 160
Shift Register when the Shift Register is empty. Then the data will be seri- ally transmitted on the TxD pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever ...
Page 161
Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the ...
Page 162
Bit 1 – RXB8: Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. • Bit ...
Page 163
Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
Page 164
Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and ...
Page 165
Examples of Baud For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- Rate Setting chronous operation can be generated by using the UBRR settings in which yield an actual baud rate differing less than 0.5% ...
Page 166
Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 0.0% ...
Page 167
Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 -0.8% ...
Page 168
Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 0.6% ...
Page 169
Two-wire Serial Interface Features • Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device Can Operate as Transmitter or Receiver • 7-bit Address Space allows up to 128 ...
Page 170
Electrical As depicted in Interconnection pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line ...
Page 171
Figure 78. START, REPEATED START, and STOP Conditions SDA SCL Address Packet All address packets transmitted on the TWI bus are nine bits long, consisting of seven address Format bits, one READ/WRITE control bit and an acknowledge bit. If the ...
Page 172
Figure 80. Data Packet Format Aggregate SDA SDA from Transmitter SDA from receiverR SCL from Master Combining Address A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and Data Packets into and a STOP ...
Page 173
The low period of the combined clock is equal to the low period of the master with the longest low period. Note that all masters listen to the SCL line, effectively starting ...
Page 174
Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure ...
Page 175
Overview of the The TWI module is comprised of several submodules, as shown in TWI Module in a thick line are accessible through the AVR data bus. Figure 84. Overview of the TWI Module SCL and SDA Pins These pins ...
Page 176
In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis- ter is not directly accessible by the ...
Page 177
TWI Register Description TWI Bit Rate Register – TWBR Bit Read/Write Initial Value • Bits [7:0] – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which ...
Page 178
START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO ...
Page 179
Bits [1:0] – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 73. TWI Bit Rate Prescaler To calculate bit rates, see used in the equation. TWI Data Register – ...
Page 180
Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts ...
Page 181
TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to ...
Page 182
Assembly code example ldi r16, (1<<TWINT)|(1<<TWSTA)| 1 (1<<TWEN) out TWCR, r16 wait1 r16,TWCR sbrs r16,TWINT rjmp wait1 in r16,TWSR 3 andi r16, 0xF8 cpi r16, START brne ERROR ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) | ...
Page 183
Transmission The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Modes Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As ...
Page 184
A START condition is sent by writing the following value to TWCR: TWCR Value TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written ...
Page 185
Table 74. Status Codes for Master Transmitter Mode $18 SLA+W has been transmitted; ACK has been received $20 SLA+W has been transmitted; NOT ACK has been received $28 Data byte has been transmitted; ACK has been received $30 Data byte ...
Page 186
Figure 87. Formats and States in the Master Transmitter Mode Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost ...
Page 187
Figure 88. Data Transfer in Master Receiver Mode SDA SCL A START condition is sent by writing the following value to TWCR: TWCR Value TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written ...
Page 188
Table 75. Status Codes for Master Receiver Mode (Continued) $08 A START condition has been transmitted $10 A repeated START condition has been transmitted $38 Arbitration lost in SLA+R or NOT ACK bit $40 SLA+R has been transmitted; ACK has ...
Page 189
Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see Figure or are masked to zero. Figure 90. Data Transfer in Slave Receiver Mode SDA SCL To initiate the Slave ...
Page 190
Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 2503Q–AVR–02/11 ATmega32(L) 190 ...
Page 191
Table 76. Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware $60 Own SLA+W has been received; ACK has been returned $68 Arbitration lost in ...
Page 192
Figure 91. Formats and States in the Slave Receiver Mode Slave Transmitter In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Mode Figure or are masked to zero. Figure 92. Data Transfer ...
Page 193
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the ...
Page 194
Table 77. Status Codes for Slave Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware $A8 Own SLA+R has been received; ACK has been returned $B0 Arbitration lost in ...
Page 195
Figure 93. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave (TWEA ...
Page 196
Combining Several In some cases, several TWI modes must be combined in order to complete the desired action. TWI Modes Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer ...
Page 197
Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the masters will know about the bus contention. ...
Page 198
Analog The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin Comparator AIN1, the Analog Comparator Output, ...
Page 199
Analog Comparator Control and Status Bit Register – ACSR Read/Write Initial Value • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be ...
Page 200
Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 79. ACIS1/ACIS0 Settings ACIS1 When ...