ATMEGA32L-8AU Atmel, ATMEGA32L-8AU Datasheet - Page 217

IC AVR MCU 32K 8MHZ 3V 44TQFP

ATMEGA32L-8AU

Manufacturer Part Number
ATMEGA32L-8AU
Description
IC AVR MCU 32K 8MHZ 3V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA32L-8AU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
TWI/SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
ATMEGA32x
Core
AVR8
Data Ram Size
2 KB
Maximum Clock Frequency
8 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
1K Bytes
Input Output
32
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
Data Rom Size
1024 B
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
10 mm
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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The ADC Data
Register – ADCL and
ADCH
ADLAR = 0
ADLAR = 1
2503Q–AVR–02/11
Table 85. ADC Prescaler Selections
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADPS2
213.
0
0
0
0
1
1
1
1
ADC7
ADC9
ADC1
15
15
R
R
R
R
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
ADPS1
R
R
R
R
6
0
0
6
0
0
0
0
1
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
5
0
0
5
0
0
ADC4
ADC6
12
12
R
R
R
R
4
0
0
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
3
0
0
3
0
0
ADC2
ADC4
10
10
R
R
R
R
2
0
0
2
0
0
ADC9
ADC1
ADC3
Division Factor
R
R
R
R
9
1
0
0
9
1
0
0
“ADC Conversion Result” on
128
16
32
64
ATmega32(L)
2
2
4
8
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
0
0
0
ADCH
ADCH
ADCL
ADCL
217

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