AT91SAM7S16-MU Atmel, AT91SAM7S16-MU Datasheet - Page 132

• Manufacturer Part Number: AT91SAM7S16-MU
• Description: MCU ARM 16K HI SPD FLASH 48-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S16-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.2.5.3
20.2.5.4
132
AT91SAM7S Series Preliminary
Flash Full Erase Command
Flash Lock Commands
Table 20-9.
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command.
However, the lock bit is automatically set at the end of the Flash write operation. As a lock region
is composed of several pages, the programmer writes to the first pages of the lock region using
Flash write commands and writes to the last page of the lock region using a Flash write and lock
command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command.
However, before programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL
commands.
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command.
Otherwise, the erase command is aborted and no page is erased.
Table 20-10. Full Erase Command
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set
Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is pro-
vided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is
activated.
Step
5
6
7
...
n
n+1
n+2
n+3
n+4
n+5
...
Step
1
2
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
...
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Handshake Sequence
Write handshaking
Write handshaking
Write Command (Continued)
MODE[3:0]
ADDR3
DATA
DATA
...
ADDR0
ADDR1
ADDR2
ADDR3
DATA
DATA
...
MODE[3:0]
CMDE
DATA
DATA[7:0]
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
Memory Address
Memory Address
Memory Address
*Memory Address++
*Memory Address++
...
DATA[15:0] or DATA[7:0]
EA
0
6175K–ATARM–30-Aug-10