AT89C5122D-PSTUM Atmel, AT89C5122D-PSTUM Datasheet - Page 175

• Manufacturer Part Number: AT89C5122D-PSTUM
• Description: IC 8051 MCU FLASH 32K 64QFN
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-PSTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Watchdog Timer
4202F–SCR–07/2008
RESET
The AT83R5122, AT8xC5122/23 microcontrollers contain a powerfull programmable
hardware Watchdog Timer (WDT) that automatically resets the chip if its software fails
to reset the WDT before the selected time interval has elapsed. It permits large timeout
ranking from 4ms to 524ms @
This WDT consist of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programmation (WDTPRG) reg-
ister. When exiting the reset, the WDT is, by default, disabled. To activate the WDT, the
user has to write the sequence 1EH and E1H into WDRST register. When the Watchdog
Timer is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or
WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at
the RST pin. The RESET pulse duration is 96xT
best use of the WDT, it should be serviced in those sections of code that will periodically
be executed within the time required to prevent a WDT reset.
The WDT is controlled by two registers (WDTRST and WDTPRG).
Figure 107. Watchdog Timer
F
CK_WD
-
-
-
WDTRST
WDTPRG
-
14-bit COUNTER
Enable
-
2
F
CK_WD
1
AT83R5122, AT8xC5122/23
= 24 MHz / X2
0
WR
Control
Decoder
OSC
, where T
7 - bit COUNTER
Outputs
OSC
=1/F
OSC
. To make the
RESET
175