AT89C5122D-PSTUM Atmel, AT89C5122D-PSTUM Datasheet - Page 133

• Manufacturer Part Number: AT89C5122D-PSTUM
• Description: IC 8051 MCU FLASH 32K 64QFN
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-PSTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Registers
4202F–SCR–07/2008
Table 77. Serial Control Register - SCON (98h)
Reset Value = 0000 0000b (Bit addressable)
Number
FE/SM0
Bit
7
6
5
4
3
2
1
0
7
Mnemonic Description
SM0
SM1
SM2
REN
RB8
TB8
Bit
FE
TI
RI
SM1
6
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 in PCON register must be set to enable access to the FE bit
Serial Port Mode bit 0 (SMOD0=0)
Refer to SM1 for serial port mode selection.
SMOD0 in PCON register must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM0
0
0
1
1
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.
This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
This bit can aslo be set by software.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 65 and Figure
66 in the other modes.
This bit can aslo be set by software.
SM2
5
SM1
0
1
0
1
AT83R5122, AT8xC5122/23
REN
4
Mode
0
1
2
3
TB8
3
9-bit UARTVariable
DescriptionBaud Rate
Shift Register F
8-bit UARTVariable
9-bit UARTF
RB8
2
CK_IDLE
Ck_IDLE
/32 or /16
/6
1
TI
RI
0
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