AT89C5122D-PSTUM Atmel, AT89C5122D-PSTUM Datasheet - Page 113

• Manufacturer Part Number: AT89C5122D-PSTUM
• Description: IC 8051 MCU FLASH 32K 64QFN
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-PSTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

USB Interrupt System
Interrupt System Priorities
Figure 62. USB Interrupt Control System
Interrupt Control System
4202F–SCR–07/2008
D+
D-
Controller
USB
Table 63. Priority Levels
As shown in Figure 63, many events can produce a USB interrupt:
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•
•
•
•
•
•
•
•
TXCMPL: Transmitted In Data (Table 70 on page 119). This bit is set by hardware
when the Host accept a In packet.
RXOUTB0: Received Out Data Bank 0 (Table 70 on page 119). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-Pong endpoints) (Table 70 on
page 119). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
RXSETUP: Received Setup (Table 70 on page 119). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
NAKIN and NAKOUT: These bits are set by hardware when a Nak Handshake has
been received on the corresponding endpoint. These bits are cleared by software.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table on page
120). This bit is set by hardware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
SOFINT: Start Of Frame Interrupt (Table 65 on page 116). This bit is set by
hardware when a USB start of frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt (Table 65 on page 116). This bit is set by
hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt (Table 65 on page 116). This bit is set by hardware when
a USB suspend is detected on the USB bus.
IPHUSB
0
0
1
1
EUSB
IEN1.6
Interrupt Enable
IEN0.7
EA
IPLUSB
0
1
0
1
AT83R5122, AT8xC5122/23
Priority Enable
IPH/L
00
01
10
11
Lowest Priority Interrupts
USB Priority Level
3 Highest
0 Lowest
1
2
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