PIC18F2510-I/SP Microchip Technology, PIC18F2510-I/SP Datasheet - Page 247

• Manufacturer Part Number: PIC18F2510-I/SP
• Description: IC MCU FLASH 16KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2510-I/SP

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 22-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 22-2:
© 2009 Microchip Technology Inc.
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1:
Name
2:
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is
disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
bit 7-1
bit 0
IPEN
Bit 7
—
SUMMARY OF WATCHDOG TIMER REGISTERS
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
bit 7
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
SBOREN
U-0
—
Bit 6
—
(1)
U-0
—
Bit 5
—
—
U-0
—
Bit 4
RI
—
U-0
—
Bit 3
TO
—
W = Writable bit
-n = Value at POR
PIC18F2X1X/4X1X
U-0
—
Bit 2
PD
—
(1)
U-0
Bit 1
POR
—
—
SWDTEN
U-0
—
Bit 0
BOR
DS39636D-page 249
(2)
SWDTEN
R/W-0
on page
Values
Reset
50
52
bit 0
(1)