PIC18F46J50-I/ML Microchip Technology, PIC18F46J50-I/ML Datasheet - Page 547

• Manufacturer Part Number: PIC18F46J50-I/ML
• Description: IC PIC MCU FLASH 64KB 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.15 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Resets .............................................................................. 413
RETFIE ............................................................................ 462
RETLW ............................................................................ 462
RETURN .......................................................................... 463
Return Address Stack ........................................................ 73
Revision History ............................................................... 537
RLCF ................................................................................ 463
RLNCF ............................................................................. 464
RRCF ............................................................................... 464
RRNCF ............................................................................ 465
RTCC
RTCEN Bit Write .............................................................. 231
S
SCKx ................................................................................ 264
SDIx ................................................................................. 264
SDOx ............................................................................... 264
SEC_IDLE Mode ................................................................ 46
SEC_RUN Mode ................................................................ 42
Serial Clock, SCKx ........................................................... 264
Serial Data In (SDIx) ........................................................ 264
Serial Data Out (SDOx) ................................................... 264
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 465
Shoot-Through Current .................................................... 257
Slave Select (SSx) ........................................................... 264
SLEEP ............................................................................. 466
Software Simulator (MPLAB SIM) .................................... 482
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ........................................... 413
SPI Mode (MSSP) ............................................................ 264
© 2009 Microchip Technology Inc.
State of Registers ...................................................... 62
Watchdog Timer (WDT) Reset ................................... 57
Brown-out Reset (BOR) ........................................... 413
Oscillator Start-up Timer (OST) ............................... 413
Power-on Reset (POR) ............................................ 413
Power-up Timer (PWRT) ......................................... 413
Associated Registers ................................................. 73
Alarm ........................................................................ 235
Alarm Value Registers (ALRMVAL) ......................... 228
Control Registers ..................................................... 221
Low-Power Modes ................................................... 236
Operation
Peripheral Module Disable (PMD) Register ............. 237
Register Interface ..................................................... 231
Register Maps .......................................................... 237
Reset ........................................................................ 236
Value Registers (RTCVAL) ...................................... 225
Associated Registers ............................................... 273
Bus Mode Compatibility ........................................... 272
Clock Speed, Interactions ........................................ 272
Configuring ...................................................... 235
Interrupt ........................................................... 236
Mask Settings .................................................. 235
Calibration ........................................................ 234
Clock Source ................................................... 232
Digit Carry Rules .............................................. 232
General Functionality ....................................... 233
Leap Year ........................................................ 233
Register Mapping ............................................. 233
Safety Window for Register Reads and Writes 233
Write Lock ........................................................ 233
Device .............................................................. 236
Power-on Reset (POR) .................................... 236
ALRMVAL ................................................ 234
RTCVAL ................................................... 234
PIC18F46J50 FAMILY
SSPOV ............................................................................ 307
SSPOV Status Flag ......................................................... 307
SSPxSTAT Register
SSx .................................................................................. 264
Stack Full/Underflow Resets .............................................. 75
SUBFSR .......................................................................... 477
SUBFWB ......................................................................... 466
SUBLW ............................................................................ 467
SUBULNK ........................................................................ 477
SUBWF ............................................................................ 467
SUBWFB ......................................................................... 468
SWAPF ............................................................................ 468
T
Table Pointer Operations (table) ...................................... 100
Table Reads/Table Writes ................................................. 75
T
TBLRD ............................................................................. 469
TBLWT ............................................................................ 470
Timer0 ............................................................................. 189
Timer1 ............................................................................. 193
Timer2 ............................................................................. 205
AD
Effects of a Reset .................................................... 272
Enabling SPI I/O ...................................................... 268
Master Mode ............................................................ 269
Master/Slave Connection ........................................ 268
Operation ................................................................. 267
Operation in Power-Managed Modes ...................... 272
Registers ................................................................. 265
Serial Clock ............................................................. 264
Serial Data In ........................................................... 264
Serial Data Out ........................................................ 264
Slave Mode .............................................................. 270
Slave Select ............................................................. 264
Slave Select Synchronization .................................. 270
SPI Clock ................................................................. 269
SSPxBUF Register .................................................. 269
SSPxSR Register .................................................... 269
Typical Connection .................................................. 268
R/W Bit ............................................................ 287, 290
Associated Registers ............................................... 191
Operation ................................................................. 190
Overflow Interrupt .................................................... 191
Prescaler ................................................................. 191
Prescaler Assignment (PSA Bit) .............................. 191
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 191
Reads and Writes in 16-Bit Mode ............................ 190
Source Edge Select (T0SE Bit) ............................... 190
Source Select (T0CS Bit) ........................................ 190
16-Bit Read/Write Mode .......................................... 198
Associated Registers ............................................... 204
Clock Source Selection ........................................... 196
Gate ......................................................................... 200
Interrupt ................................................................... 199
Operation ................................................................. 196
Oscillator .......................................................... 193, 198
Resetting, Using the ECCP Special Event Trigger .. 200
TMR1H Register ...................................................... 193
TMR1L Register ...................................................... 193
Use as a Clock Source ............................................ 199
Associated Registers ............................................... 206
Interrupt ................................................................... 206
Operation ................................................................. 205
.................................................................................. 347
Open-Drain Output Option ............................... 267
Switching Assignment ..................................... 191
Layout Considerations ..................................... 199
DS39931C-page 547