PIC18F46J50-I/ML Microchip Technology, PIC18F46J50-I/ML Datasheet
PIC18F46J50-I/ML
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PIC18F46J50-I/ML Summary of contents
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... Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18F46J50 family silicon revisions are shown in Table 1. Revision ID for Silicon Revision (1) Device ID ...
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... PIC18F46J50 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Number 2 MSSP I C™ Modes 2 MSSP I C Slave EUSART Enable/Dis- able A OSC Clock PMP PSP Low-Power Deep Sleep modes DC Supply Volt- Characteristics age A/D Band Gap Reference CTMU Constant Current Note 1: Only those issues indicated in the last column apply to the current silicon revision. ...
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... Affected Silicon Revisions 2010 Microchip Technology Inc. PIC18F46J50 FAMILY 2. Module: Master Synchronous Serial Port (MSSP) In extremely rare cases, when configured for I slave reception, the MSSP module may not receive the correct data. This occurs only if the Serial ...
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... PIC18F46J50 FAMILY 3. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In rare situations, when interrupts are enabled, unexpected results may occur if: • The EUSART is disabled (the SPEN bit, RCSTAx<7> • The EUSART is re-enabled (RCSTAx<7> • A two-cycle instruction is executed immediately after setting SPEN = 1 ...
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... OSC 001 Affected Silicon Revisions 2010 Microchip Technology Inc. PIC18F46J50 FAMILY 5. Module: Parallel Master Port (PMP) When (PMMODEH<1:0> and PMPEN = 1), the data bus (PMD<7:0>) may not work correctly and incorrect data could be captured into the PMDIN1L register. Work around None. ...
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... PIC18F46J50 FAMILY 6. Module: Low-Power Modes (Deep Sleep) Entering Deep Sleep mode takes approximately following the SLEEP instruction. Wake-up CY events that occur during this Deep Sleep entry period may not generate a wake-up event. Work around If using the RTCC alarm for Deep Sleep wake-up, ...
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... Affected Silicon Revisions 2010 Microchip Technology Inc. PIC18F46J50 FAMILY 9. Module: Charge Time Measurement Unit ) parameter On an “F” device, the CTMU current source will stop DD sourcing current if the applied V below the LVDSTAT (WDTCON<6>) threshold (2.45V nominal). When V threshold, the CTMU will function normally. This issue does not apply to “ ...
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... PIC18F46J50 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the Device Data Sheet (DS39931C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Special Features (CONFIG2L) The “ ...
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... Removed silicon issue 1 (Special Features, T1DIG) and modified decremented issue 2 (MSSP1) and 6 (Low-Power Modes – Deep Sleep). Added data sheet clarifications 1 (Special Features – CONFIG2L), 2 (DC Characteristics – Power-Down Current) and 3 (DC Characteristics – Input Leakage). 2010 Microchip Technology Inc. PIC18F46J50 FAMILY 5 (ADC), 1, formerly DS80436C-page 9 ...
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... PIC18F46J50 FAMILY NOTES: DS80436C-page 10 2010 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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