DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 4

• Manufacturer Part Number: DSPIC30F2010-20I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/MMG; DSPIC30F201020IMM; DSPIC30F201020IMM

dsPIC30F2010
TABLE 2:
DS80451E-page 4
Note 1:
EEPROM
EEPROM
Controller
Program
Interrupt
Memory
Module
Sleep
Mode
Flash
Data
Data
ADC
QEI
QEI
Only those issues indicated in the last column apply to the current silicon revision.
Accumulation
Accumulation
Consumption
Timer Gated
Timer Gated
Write/Erase
Operation
Operation
I
PD
SILICON ISSUE SUMMARY (CONTINUED)
Feature
in Sleep
Current
Current
RTSP
Mode
Mode
Mode
—
—
Sleep
Number
Item
32.
33.
34.
35.
36.
37.
38.
39.
Write/Erase operations performed on Data EEPROM
need to be timed by the application software. Self-timed
write operations are not supported.
When a device Reset occurs while an RTSP operation
is in progress, code execution may lead to an Address
Error trap.
Data EEPROM is operational at a device throughput of
up to 25 MIPS.
A specific write sequence for the Interrupt Priority
Control 2 (IPC2) Special Function Register (SFR) is
required.
The device exhibits I
certain work arounds are required to achieve I
range.
When Timer Gated Accumulation is enabled, the QEI
module does not generate an interrupt on every falling
edge.
When Timer Gated Accumulation is enabled, and an
external signal is applied, the POSCNT increments and
generates an interrupt after a match with MAXCNT.
If the ADC module is in an enabled state when the
device enters Sleep Mode, the power-down current
(I
specifications.
PD
) of the device may exceed the device data sheet
Issue Summary
PD
less than 0.1 μA. However,
PD
© 2010 Microchip Technology Inc.
in this
A0 A1 A2 A3 A4
X
X
X
X
X
X
X
X
Revisions
X
X
X
Affected
X
X
X
X
X
X
(1)
X
X
X