DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 21

• Manufacturer Part Number: DSPIC30F2010-20I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/MMG; DSPIC30F201020IMM; DSPIC30F201020IMM

35. Module: Interrupt Controller
EXAMPLE 18:
EXAMPLE 19:
© 2010 Microchip Technology Inc.
mov
mov
disi #2
mov
mov
asm volatile(
//Note: There are no commas between
//
//
A specific write sequence for the Interrupt Priority
Control 2 (IPC2) SFR is required to prevent
possible data corruption in the Interrupt Enable
Control 2 (IEC2) SFR. Interrupts must be disabled
during this IPC2 SFR write sequence.
Work around
An example of this write sequence is shown in
Example
When coding in C, the write sequence shown
above can be implemented using inline Assembly
instructions. The equivalent write sequence using
the MPLAB C Compiler for dsPIC DSCs is shown
in
Affected Silicon Revisions
A0
#IPC2, w0
#0x4444, w1
w1, IPC2
#IPC2, w0
X
Example
the quoted strings in the code
segment above.
A1
18.
19.
A2
“push.d
“mov
“mov
“disi #2\n\t”
“mov
“mov
“pop.d
;Point w0 to IPC2
;Write data to go to IPC2
;Disable interrupts for
;next two cycles
;Write the data to IPC2
;Target w1 to keep IPC2
;address on bus
A3
#IPC2,w0\n\t”
#0x4444,w1\n\t”
w1, IPC2\n\t”
#IPC2, w0\n\t”
w0”);
w0\n\t”
A4
36. Module: Sleep Mode
EXAMPLE 20:
37. Module: QEI
The device exhibits I
Work around
If the application does not use the on-chip A/D
converter, it is possible to reduce the I
below 0.1 μA. The following additional measures
need to be taken in these circumstances:
1. In the application hardware, the V
2. In the application software, the code sequence
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
.include “p30f2010.inc”
.......
BCLR
MOV
MOV
BCLR
PWRSAV #SLEEP_MODE
A0
A0
X
X
pin (pin 2) on the dsPIC30F2010 should be
connected to the circuit ground (GND).
shown in
bring the device into the power-saving Sleep
mode.
A1
A1
X
ADCON1, #ADON
#0x2000, W0
W0, ADCON2
PMD1, #ADCMD
dsPIC30F2010
Example 20
A2
A2
X
A3
A3
PD
X
of approximately 100 μA.
A4
A4
should be executed to
X
;Required code
;sequence for
;low power-down
;current.
;Device enters
;SLEEP mode here
DS80451E-page 21
PD
REF
to values
+/RB0