DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 20

• Manufacturer Part Number: DSPIC30F2010-20I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/MMG; DSPIC30F201020IMM; DSPIC30F201020IMM

dsPIC30F2010
32. Module: Data EEPROM
EXAMPLE 16:
DS80451E-page 20
;The following code example assumes that the
;Write-latches have been pre-loaded and
;Timer1 has been set up to interrupt at the
;end of the write/erase cycle.
L1: BTSS
__T1Interrupt:
When performing write/erase operations on Data
EEPROM, the device automatically times the
write/erase operation. For this revision of silicon,
this method of timing the erase/write operation is
not supported.
Note that this erratum does not affect writing to
Data EEPROM using a device programmer, such
as MPLAB ICD 2 or PRO MATE.
Work around
When updating Data EEPROM, the write cycle
time must be controlled using an on-chip timer
resource. Setting the TWRI bit (NVMCON<8>) to
a logic ‘1’ enables the Data EEPROM write cycle
time to be terminated by the next acknowledged
interrupt source. Therefore, the user must ensure
that a single timer is configured to generate a CPU
recognized interrupt and terminate the write cycle.
The timer cycle should be set for a value greater
than 2 ms but less than 5 ms.
Example 16
similar work around may be applied for an erase
operation.
Affected Silicon Revisions
CLR
CLR
BSET
DISI
MOV
MOV
MOV
MOV
MOV
MOV
BSET
NOP
NOP
BRA
BCLR
......
SETM
BCLR
RETFIE
A0
X
A1
MyFlag
TMR1
T1CON, #TON
#8
#0X4105, W0
W0, NVMCON
#0X55, W0
W0, NVMKEY
#0XAA, W0
W0, NVMKEY
NVMCON, #WR
MyFlag, #0
L1
T1CON, #TON
MyFlag
IFS0, #T1IF
demonstrates this work around. A
A2
A3
A4
;Clear a flag
;Clear Timer1
;Turn Timer1 On
;Load NVMCON with
;bit8 set
;Perform Unlock
;sequence
;Set the WR bit
;Optionally, wait
;for flag set
;by Timer1 ISR
;Turn off Timer1
;Continue
;Timer1 ISR
;Set a flag
;Clear T1IF and
;return from ISR
33. Module: Program Flash Memory
EXAMPLE 17:
34. Module: Data EEPROM
__AddressError:
If a device Reset occurs while an RTSP operation
is in progress, code execution after the reset may
lead to an Address Error Trap.
Work around
The user should define an address Error Trap Ser-
vice Routine as shown in
resume normal code execution.
Affected Silicon Revisions
At device throughput greater than 25 MIPS, read
operations performed on Data EEPROM may not
function correctly.
Work around
When reading data from Data EEPROM, the
application should perform a clock-switch operation
to lower the frequency of the system clock so that
the throughput is less than 25 MIPS. This may be
easily performed at any time via the Oscillator
Postscaler bits (POST), (OSCCON<7:6>), that
allow the application to divide the system clock
down by a factor of 4, 16 or 64.
Affected Silicon Revisions
bclr
bclr
reset
A0
A0
X
X
A1
A1
RCON, #TRAPR
INTCON1, #ADDRERR
A2
A2
© 2010 Microchip Technology Inc.
A3
A3
Example 17
A4
A4
;Clear the Trap
;Reset Flag Bit
;Address Error
;trap flag bit
;Software reset
;Clear the
in order to