DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F2010-20I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/MMG; DSPIC30F201020IMM; DSPIC30F201020IMM

dsPIC30F2010
11. Module: ADC
12. Module: ADC
DS80451E-page 10
Sampling multiple channels sequentially using
any conversion trigger source other than the
auto-convert feature requires the SAMC bits to
be
conditions are all satisfied, the module may not
operate as specified:
- Multiple S&H channels are sampled sequentially
- Auto-convert option is not chosen as the
- SAMC (ADCON3<12:8>) is equal to ‘00000’
Work around
Set the value of the SAMC bits to anything other
than ‘00000’. The ADC module will now operate
as specified.
Affected Silicon Revisions
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPIx
bits are non-zero. This implies that if the ADC is
configured to generate an interrupt after a certain
number of INT0 triggered conversions, the ADC
conversions will not be triggered and the device
will remain in Sleep. The ADC will perform
conversions and wake-up the device only if it is
configured to generate an interrupt after each INT0
triggered conversion (SMPI<3:0> = 0000).
Work around
None. If an ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> to ‘0000’ (interrupt
on every conversion).
Affected Silicon Revisions
A0
A0
X
X
CHPS (ADCON2<9:8>) is not equal to ‘00’ and
SIMSAM (ADCON1<3>) = 0
conversion trigger
SSRC (ADCON1<7:5>) is not equal to ‘111’
non-zero.
A1
A1
X
X
A2
A2
X
X
Therefore,
A3
A3
X
X
A4
A4
X
X
if
the
following
13. Module: Watchdog Timer
14. Module: PLL
The Watchdog Timer does not function as
specified. If the CLRWDT instruction is not executed
before the Watchdog Timer is half-expired or
greater, the device will reset.
Work around
The user must always issue the CLRWDT instruction
before the Watchdog Timer is half-expired. For
instance, if the Watchdog time-out period is config-
ured for 2 ms, the CLRWDT instruction must be
executed faster than every 1 ms.
Affected Silicon Revisions
When the 4x PLL mode of operation is selected, the
specified input frequency range of 4 MHz-10 MHz is
not fully supported.
When device V
frequency must be in the range of 4 MHz-5 MHz.
When device V
frequency must be in the range of 4 MHz-6 MHz
for both industrial and extended temperature
ranges.
Work around
1. Use 8x PLL or 16x PLL mode of operation and
2. Use the EC without PLL Clock mode with a
Affected Silicon Revisions
A0
A0
X
X
set final device clock speed using the
POST<1:0> Oscillator Postscaler Control bits
(OSCCON<7:6>).
suitable
equivalent 4x PLL clock rate.
A1
A1
X
X
clock
A2
A2
X
X
DD
DD
is 2.5V-3.0V, the 4x PLL input
is 3.0V-3.6V, the 4x PLL input
© 2010 Microchip Technology Inc.
A3
A3
X
X
frequency
A4
A4
X
X
to
obtain
the