PIC18LF44J50-I/ML Microchip Technology, PIC18LF44J50-I/ML Datasheet - Page 548
![IC PIC MCU FLASH 16K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF44J50-I/ML
Manufacturer Part Number
PIC18LF44J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F46J50 FAMILY
Timer3 .............................................................................. 207
Timer4 .............................................................................. 217
Timing Diagrams
DS39931C-page 548
Output ...................................................................... 206
16-Bit Read/Write Mode ........................................... 211
Associated Registers ............................................... 215
Gate ......................................................................... 211
Operation ................................................................. 210
Oscillator .......................................................... 207, 211
Overflow Interrupt ............................................ 207, 215
Special Event Trigger (ECCP) ................................. 215
TMR3H Register ...................................................... 207
TMR3L Register ....................................................... 207
Associated Registers ............................................... 218
Interrupt .................................................................... 218
MSSP Clock Shift ..................................................... 218
Operation ................................................................. 217
Output ...................................................................... 218
Postscaler. See Postscaler, Timer4.
PR4 Register ............................................................ 217
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 217
TMR4 to PR4 Match Interrupt .......................... 217, 218
A/D Conversion ........................................................ 522
Asynchronous Reception ......................................... 330
Asynchronous Transmission .................................... 328
Asynchronous Transmission (Back-to-Back) ........... 328
Automatic Baud Rate Calculation ............................ 326
Auto-Wake-up Bit (WUE) During Normal Operation 331
Auto-Wake-up Bit (WUE) During Sleep ................... 331
Baud Rate Generator with Clock Arbitration ............ 305
BRG Overflow Sequence ......................................... 326
BRG Reset Due to SDAx Arbitration During Start Condi-
Bus Collision During a Repeated Start Condition (Case
Bus Collision During a Repeated Start Condition (Case
Bus Collision During a Start Condition (SCLx = 0) ... 313
Bus Collision During a Stop Condition (Case 1) ...... 315
Bus Collision During a Stop Condition (Case 2) ...... 315
Bus Collision During Start Condition (SDAx Only) ... 312
Bus Collision for Transmit and Acknowledge ........... 311
CLKO and I/O .......................................................... 507
Clock Synchronization ............................................. 298
Clock/Instruction Cycle .............................................. 76
Enhanced Capture/Compare/PWM ......................... 510
EUSARTx Synchronous Receive (Master/Slave) .... 521
EUSARTx Synchronous Transmission (Master/Slave) ..
Example SPI Master Mode (CKE = 0) ..................... 513
Example SPI Master Mode (CKE = 1) ..................... 514
Example SPI Slave Mode (CKE = 0) ....................... 515
Example SPI Slave Mode (CKE = 1) ....................... 516
External Clock .......................................................... 505
Fail-Safe Clock Monitor ............................................ 428
First Start Bit ............................................................ 305
Full-Bridge PWM Output .......................................... 252
Half-Bridge PWM Output ................................. 250, 257
High/Low-Voltage Detect Characteristics ................ 503
High-Voltage Detect (VDIRMAG = 1) ....................... 395
I
I
I
I
2
2
2
2
2C Bus Data .......................................................... 517
C Acknowledge Sequence .................................... 310
C Bus Start/Stop Bits ............................................. 517
C Master Mode (7 or 10-Bit Transmission) ........... 308
tion ................................................................... 313
1) ...................................................................... 314
2) ...................................................................... 314
521
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 394
MSSPx I
MSSPx I
Parallel Master Port Read ........................................ 511
Parallel Master Port Write ........................................ 512
Parallel Slave Port Read .................................. 173, 175
Parallel Slave Port Write .................................. 173, 176
PWM Auto-Shutdown with Auto-Restart Enabled .... 256
PWM Auto-Shutdown with Firmware Restart .......... 256
PWM Direction Change ........................................... 253
PWM Direction Change at Near 100% Duty Cycle .. 254
PWM Output ............................................................ 244
PWM Output (Active-High) ...................................... 248
PWM Output (Active-Low) ....................................... 249
Read and Write, 8-Bit Data, Demultiplexed Address 180
Read, 16-Bit Data, Demultiplexed Address ............. 183
Read, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit
Read, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
Read, 8-Bit Data, Fully Multiplexed 16-Bit Address . 182
Read, 8-Bit Data, Partially Multiplexed Address ...... 180
Read, 8-Bit Data, Partially Multiplexed Address, Enable
Read, 8-Bit Data, Wait States Enabled, Partially Multi-
Repeated Start Condition ........................................ 306
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................ 332
Slave Synchronization ............................................. 270
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 269
SPI Mode (Slave Mode, CKE = 0) ........................... 271
SPI Mode (Slave Mode, CKE = 1) ........................... 271
Steering Event at Beginning of Instruction (STRSYNC =
Steering Event at End of Instruction (STRSYNC = 0) ...
Synchronous Reception (Master Mode, SREN) ...... 335
Synchronous Transmission ..................................... 333
Synchronous Transmission (Through TXEN) .......... 334
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Tied to V
Timer Pulse Generation ........................................... 236
Timer0 and Timer1 External Clock .......................... 509
2
2
2
2
2
2
2
2
2
2
2
C Master Mode (7-Bit Reception) .......................... 309
C Slave Mode (10-Bit Reception, SEN = 0, ADMSK =
C Slave Mode (10-Bit Reception, SEN = 0) .......... 295
C Slave Mode (10-Bit Reception, SEN = 1) .......... 300
C Slave Mode (10-Bit Transmission) .................... 296
C Slave Mode (7-Bit Reception, SEN = 0, ADMSK =
C Slave Mode (7-Bit Reception, SEN = 0) ............ 291
C Slave Mode (7-Bit Reception, SEN = 1) ............ 299
C Slave Mode (7-Bit Transmission) ...................... 293
C Slave Mode General Call Address Sequence (7 or
C Stop Condition Receive or Transmit Mode ........ 310
01001) ............................................................. 294
01011) ............................................................. 292
10-Bit Addressing Mode) ................................. 301
Address ........................................................... 184
dress ................................................................ 183
Strobe .............................................................. 181
plexed Address ................................................ 180
(OST) and Power-up Timer (PWRT) ............... 508
1) ..................................................................... 260
260
V
V
V
............................................................................ 61
DD
DD
DD
2
2
), Case 1 ..................................................... 61
), Case 2 ..................................................... 61
C Bus Data ............................................... 519
C Bus Start/Stop Bits ............................... 519
Rise < T
PWRT
© 2009 Microchip Technology Inc.
) ............................................ 60
DD
, V
DD
Rise > T
PWRT
DD
)
,
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