PIC18LF44J50-I/ML Microchip Technology, PIC18LF44J50-I/ML Datasheet - Page 140
![IC PIC MCU FLASH 16K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF44J50-I/ML
Manufacturer Part Number
PIC18LF44J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F46J50 FAMILY
TABLE 9-9:
TABLE 9-10:
DS39931C-page 140
PORTD
LATD
TRISD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1:
RD3/PMD3/
RP20
RD4/PMD4/
RP21
RD5/PMD5/
RP22
RD6/PMD6/
RP23
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
RD7/PMD7/
RP24
Name
(1)
Pin
(1)
(1)
These registers are not available in 28-pin devices.
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TRISD7
LATD7
Bit 7
RD7
PORTD I/O SUMMARY (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Function
PMD3
PMD4
PMD5
PMD6
PMD7
RP20
RP21
RP22
RP23
RP24
RD3
RD4
RD5
RD6
RD7
TRISD6
LATD6
Bit 6
RD6
Setting
TRIS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
TRISD5
LATD5
Bit 5
RD5
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL Parallel Master Port data in.
Type
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
TRISD4
LATD4
Bit 4
RD4
PORTD<3> data input.
LATD<3> data output.
Parallel Master Port data out.
Remappable peripheral pin 20 input.
Remappable peripheral pin 20 output.
PORTD<4> data input.
LATD<4> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 21 input.
Remappable peripheral pin 21 output.
PORTD<5> data input.
LATD<5> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 22 input.
Remappable peripheral pin 22 output.
PORTD<6> data input.
LATD<6> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 23 input.
Remappable peripheral pin 23 output.
PORTD<7> data input.
LATD<7> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 24 input.
Remappable peripheral pin 24 output.
TRISD3
LATD3
Bit 3
RD3
TRISD2
LATD2
Bit 2
RD2
Description
TRISD1
LATD1
Bit 1
RD1
© 2009 Microchip Technology Inc.
2
C/SMB = I
TRISD0
LATD0
Bit 0
RD0
2
C/SMBus
on page
Values
Reset
86
86
86
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