PIC18LF44J50-I/ML Microchip Technology, PIC18LF44J50-I/ML Datasheet - Page 287
![IC PIC MCU FLASH 16K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF44J50-I/ML
Manufacturer Part Number
PIC18LF44J50-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF44J50-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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18.5.2
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I
operation. Four mode selection bits (SSPxCON1<3:0>)
allow one of the following I
• I
• I
• I
• I
• I
• I
Selection of any I
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISB or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
18.5.3
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISB<5:4> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I
interrupt on an address match. Address masking will
allow the hardware to generate an interrupt for more
than one address (up to 31 in 7-bit addressing and up
to 63 in 10-bit addressing). Through the mode select
bits, the user can also choose to interrupt on Start and
Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
• The overflow bit, SSPOV (SSPxCON1<6>), was
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but bit SSPxIF is set. The BF bit is
cleared by reading the SSPxBUF register, while bit
SSPOV is cleared through software.
© 2009 Microchip Technology Inc.
Stop bit interrupts enabled
Stop bit interrupts enabled
Idle
before the transfer was received.
set before the transfer was received.
2
2
2
2
2
2
C Master mode, clock
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address) with Start and
C Slave mode (10-bit address) with Start and
C Firmware Controlled Master mode, slave is
2
C Slave mode hardware will always generate an
OPERATION
SLAVE MODE
2
C mode with the SSPEN bit set
2
C modes to be selected:
2
C
PIC18F46J50 FAMILY
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I
MSSP module, are shown in timing parameter 100 and
parameter 101.
18.5.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register, SSPxSR<7:1>,
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
addressing is as follows, with steps 7 through 9 for the
slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
2
C specification, as well as the requirement of the
The SSPxSR register value is loaded into the
SSPxBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
The MSSPx Interrupt Flag bit, SSPxIF, is set
(and interrupt is generated, if enabled) on the
falling edge of the ninth SCLx pulse.
Receive first (high) byte of address (bits,
SSPxIF, BF and UA, are set on address match).
Update the SSPxADD register with second (low)
byte of address (clears bit, UA, and releases the
SCLx line).
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Receive second (low) byte of address (bits,
SSPxIF, BF and UA, are set).
Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit, UA.
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits,
SSPxIF and BF, are set).
Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
Addressing
DS39931C-page 287
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