PIC16C770-I/SO Microchip Technology, PIC16C770-I/SO Datasheet - Page 78

• Manufacturer Part Number: PIC16C770-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C770I/SO

PIC16C717/770/771
9.2
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine when the bus is free (multi-
master function). The MSSP module implements the
Standard mode specifications, as well as 7-bit and 10-
bit addressing.
Two pins are used to transfer data. They are the SCL
pin (clock) and the SDA pin (data). The MSSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>). The SCL and SDA pins are
"glitch" filtered when operating as inputs. This filter
functions in both the 100 kHz and 400 kHz modes.
When these pins operate as outputs in the 100 kHz
mode, there is a slew rate control of the pin that is inde-
pendent of device frequency.
Before selecting any I
must be programmed as inputs by setting the appropri-
ate TRIS bits. This allows the MSSP module to configure
and drive the I/O pins as required by the I
The MSSP module has six registers for I
They are listed below.
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP STATUS Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SSPCON register allows for control of the I
operation. Four mode selection bits (SSPCON<3:0>)
configure the MSSP as any one of the following I
modes:
• I
• I
• I
• I
• I
• Firmware Controlled Master mode
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit. It specifies whether the
received byte was data or address, if the next byte is
the completion of 10-bit address, and if this will be a
read or write data transfer.
SSPBUF is the register to which the transfer data is
written, and from which the transfer data is read. The
SSPSR register shifts the data in or out of the device.
In receive operations, the SSPBUF and SSPSR create
a doubled, buffered receiver. This allows reception of
the next byte to begin before reading the last byte of
received data. When the complete byte is received, it is
DS41120B-page 76
SCL Freq = F
(7-bit address)
(10-bit address)
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Master mode
C Slave mode with START and STOP interrupts
C Slave mode with START and STOP interrupts
MSSP I
OSC
2
/ [4 (SSPADD + 1)]
C Operation
2
C mode, the SCL and SDA pins
2
C mode fully implements all
2
2
C protocol.
C operation.
Advance Information
2
2
C
C
transferred from the SSPSR register to the SSPBUF
register and flag bit SSPIF is set. If another complete
byte is received before the SSPBUF register is read a
receiver overflow occurs, in which case, the SSPOV bit
(SSPCON<6>) is set and the byte in the SSPSR is lost.
FIGURE 9-7:
9.2.1
The MSSP module includes three SSP modes of oper-
ation to maintain upward compatibility with the SSP
module. These modes are:
• Firmware controlled Master mode (slave idle)
• 7-bit Slave mode with START and STOP
• 10-bit Slave mode with START and STOP
The firmware controlled Master mode enables the
START and STOP condition interrupts but all other I
functions are generated through firmware including:
• Generating the START and STOP conditions
• Generating the SCL clock
• Supplying the SDA bits in the proper time and
In firmware controlled Master mode, the SCL and SDA
lines are manipulated by clearing and setting the corre-
sponding TRIS bits. The output level is always low irre-
spective of the value(s) in the PORT register. A ‘1’ is
output by setting the TRIS bit and a ‘0’ is output by
clearing the TRIS bit
The 7-bit and 10-bit Slave modes with START and
STOP condition interrupts operate identically to the
MSSP Slave modes except that START and STOP
conditions generate SSPIF interrupts.
RB2/SCK/
RB4/SDI/
condition interrupts.
condition interrupts.
phase relationship to the SCL signal.
SDA
SCL
UPWARD COMPATIBILITY WITH
SSP MODULE
Read
Clock
Shift
I
DIAGRAM
2
C SLAVE MODE BLOCK
MSb
STOP bit detect
Match detect
SSPADD reg
SSPBUF reg
START and
SSPSR reg
2002 Microchip Technology Inc.
LSb
Write
(SSPSTAT reg)
Internal
Data Bus
Set, RESET
S, P bits
Addr Match
2
C