PIC16C770-I/SO Microchip Technology, PIC16C770-I/SO Datasheet - Page 77

• Manufacturer Part Number: PIC16C770-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C770I/SO

9.1.7
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the SSPIF
interrupt flag bit will be set and if enabled will wake the
device from SLEEP.
TABLE 9-1:
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the MSSP in SPI mode.
10Bh,18Bh
2002 Microchip Technology Inc.
0Bh, 8Bh,
Address
0Ch
8Ch
9Dh
13h
14h
94h
86h
SLEEP OPERATION
SSPSTAT
SSPCON
SSPBUF
INTCON
ANSEL
TRISB
Name
PIR1
PIE1
REGISTERS ASSOCIATED WITH SPI OPERATION
WCOL
Bit 7
SMP
GIE
—
—
SSPOV
PEIE
ADIF
ADIE
Bit 6
CKE
Synchronous Serial Port Receive Buffer/Transmit Register
SSPEN
Advance Information
Bit 5
T0IE
D/A
—
—
INTE
Bit 4
CKP
—
—
P
SSPM3
SSPIE
SSPIF
RBIE
Bit 3
S
9.1.8
A RESET disables the MSSP module and terminates
the current transfer.
PIC16C717/770/771
CCP1IF
CCP1IE
SSPM2
Bit 2
T0IF
R/W
EFFECTS OF A RESET
TMR2IF
TMR2IE
SSPM1
INTF
Bit 1
UA
TMR1IF
TMR1IE
SSPM0
RBIF
Bit 0
BF
0000 000x
-0-- 0000
-0-- 0000
xxxx xxxx
0000 0000
0000 0000
--11 1111
1111 1111
POR, BOR
DS41120B-page 75
MCLR, WDT
0000 000u
-0-- 0000
-0-- 0000
uuuu uuuu
0000 0000
0000 0000
--11 1111
1111 1111