PIC16C770-I/SO Microchip Technology, PIC16C770-I/SO Datasheet - Page 131

• Manufacturer Part Number: PIC16C770-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C770I/SO

12.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This oscillator is independent from the processor clock.
If enabled, the WDT will run even if the main clock of
the device has been stopped, for example, by execu-
tion of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
FIGURE 12-11:
TABLE 12-7:
Address
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for the full description of the configuration word bits.
Note 1: PSA and PS<2:0> are bits in the OPTION_REG register.
2002 Microchip Technology Inc.
2: WDTE bit in the configuration word.
Name
Config. bits
OPTION_REG
SUMMARY OF WATCHDOG TIMER REGISTERS
WATCHDOG TIMER BLOCK DIAGRAM
Enable Bit
WDT Timer
(1)
WDT
RBPU
From TMR0 Clock Source
( Figure 5-2 )
Bit 7
(2)
—
INTEDG
BODEN
Bit 6
0
1
M
U
X
PSA
MCLRE
T0CS
Bit 5
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by program-
ming the configuration bit WDTE to ’0’ (Section 12.1).
WDT time-out period values may be found in Table 15-
4. Values for the WDT prescaler may be assigned using
the OPTION_REG register.
0
PWRTE
Note:
T0SE
Bit 4
PIC16C717/770/771
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
The SLEEP instruction clears the WDT and
the postscaler, if assigned to the WDT,
restarting the WDT period.
1
8
WDTE
Bit 3
PSA
PSA
To TMR0 ( Figure 5-2 )
FOSC2
(1)
Bit 2
PS2
PS<2:0>
FOSC1
(1)
DS41120B-page 129
Bit 1
PS1
FOSC0
Bit 0
PS0