AT90PWM3B-16SU Atmel, AT90PWM3B-16SU Datasheet - Page 350

• Manufacturer Part Number: AT90PWM3B-16SU
• Description: IC MCU AVR RISC 8K FLASH 32-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3B-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• On-chip Dac: 1-chx10-bit
• Controller Family/series: AVR PWM
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32.2
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AT90PWM2B/3B
AT90PWM2/3/2B/3B
15. PSC : Autolock mode
16. DALI : 17th bit detection
17. PSC : One ramp mode with PSC input mode 8
18. PSC : Desactivation of outputs in mode 14
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1. PSC : Double End-Of-Cycle Interrupt Request in Centered Mode
2. ADC : Conversion accuracy
3. DAC Driver linearity above 3.6V
The comparator output toggles at the comparator clock frequency when the voltage differ-
ence between both inputs is lower than the offset. This may occur when comparing signal
with small slew rate.
Work around:
This effect normally do not impact the PSC, as the transition is sampled once per PSC cycle
Be carefull when using the comparator as an interrupt source.
This mode is not properly handled when CLKPSC is different from CLK IO.
Work around:
With CLKPSC equals 64/32 MHz (CLKPLL), use LOCK mode
17th bit detection do not occurs if the signal arrives after the sampling point.
Workaround:
Use this feature only for sofware development and not in field conditions
The retriggering is not properly handled in this case.
Work around:
Do not program this case.
See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output” on
page 154.
Work around:
Do not use this mode to desactivate output if retrigger event do not occurs during On-Time.
PSC : Double End-Of-Cycle Interrupt Request in Centered Mode
ADC : Conversion accuracy
In centered mode, after the “expected” End-Of-Cycle Interrupt, a second unexpected Inter-
rupt occurs 1 PSC cycle after the previous interrupt.
Work around:
While CPU cycle is lower than PSC clock, the CPU sees only one interrupt request. For PSC
clock period greater than CPU cycle, the second interrupt request must be cleared by
software.
The conversion accuracy degrades when the ADC clock is 2 MHz.
Work around:
When a 10 bit conversion accuracy is required, use an ADC clock of 1 MHz or below.
At 2 Mhz the ADC can be used as a 7 bits ADC.
With 5V Vcc, the DAC driver linearity is poor when DAC output level is above Vcc-1V. At 5V,
DAC output for 1023 will be around 5V - 40mV.
Work around: .
4317J–AVR–08/10