AT90PWM3B-16SU Atmel, AT90PWM3B-16SU Datasheet - Page 224

• Manufacturer Part Number: AT90PWM3B-16SU
• Description: IC MCU AVR RISC 8K FLASH 32-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3B-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• On-chip Dac: 1-chx10-bit
• Controller Family/series: AVR PWM
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.6.5
224
AT90PWM2/3/2B/3B
EUSART Status Register C – EUCSRC
When set the EUSART operates in manchester encoder/decoder mode (Manchester encoded
frames). When cleared the EUSART detected and transmit level encoded frames.
Table 19-4.
As in Manchester mode the parity checker and generator are unavailable, the parity
should be configured to none ( write UPM1:0 to 00 in UCSRC), see Table 18-5.
• Bit 0 –Bit Order
This bit allows to change the bit ordering in the transmit and received frames.
Clear to transmit and receive LSB first (standard USART mode)
Set to transmit and receive MSB first.
• Bit 7:4 –Reserved Bits
These bits are reserved for future use. For compatibilty with future devices, these bits must be
written to zero when EUSCRC is written.
• Bit 3 –Frame Error Manchester
This bit is set by hardware when a framing error is detected in manchester mode. This bit is valid
when the RxC bit is set and until the receive buffer (UDR) is read.
• Bit 2 –F1617
When the receiver is configured for 16 or 17 bits in Manchester encoded mode, this bit indicates
if the received frame is 16 or 17 bits lenght.
Cleared: indicates that the received frame is 16 bits lenght.
Set: Indicates that the received frame is 17 bits lenght.
This bit is valid when the RxC bit is set and until the receive buffer (UDR) is read.
• Bit 1:0 –Stop bits values
When Manchester mode is activated, these bits contains the stop bits value of the previous
received frame.
When the data bits in the serial frame are standard level encoded, these bits are not updated.
Bit
Read/Write
Initial Value
UMSEL
0
1
0
0
1
1
USART/EUSART modes selection summary
EMCH
R
7
0
-
X
X
0
1
0
1
R
6
0
EUSART
-
0
0
1
1
1
1
R
5
0
-
Mode
Asynchronous up to 9 bits level encoded (standard
asynchronous USART mode)
Synchronous up to 9 bits level encoded (standard
synchronous USART mode)
Asynchronous up to 17 bits level encoded
Asynchronous up to 17 bits Manchester encoded
Synchronous up to 17 bits level encoded
Reserved
R
4
0
-
FEM
R
3
0
F1617
R
2
0
STP1
R
1
0
STP0
R
0
0
4317J–AVR–08/10
EUCSRC