PIC18F26J11-I/SO Microchip Technology, PIC18F26J11-I/SO Datasheet - Page 83
![IC PIC MCU FLASH 64K 2V 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F26J11-I/SO
Manufacturer Part Number
PIC18F26J11-I/SO
Description
IC PIC MCU FLASH 64K 2V 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F26J11-I/SO
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 83 of 528
- Download datasheet (8Mb)
5.3.4.1
There are several registers that share the same
address in the SFR space. The register’s definition and
usage depends on the operating mode of its associated
peripheral. These registers are:
• SSPxADD and SSPxMSK: These are two
TABLE 5-4:
© 2009 Microchip Technology Inc.
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
Legend:
Note
separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 18.5.3.4 “7-Bit
Address Masking Mode” for additional details.
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
Context Defined SFRs
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
GIE/GIEH
STKFUL
INT2IP
RBPU
Bit 7
—
—
—
—
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
PEIE/GIEL
INTEDG0
STKUNF
INT1IP
Bit 6
—
—
—
—
INTEDG1
TMR0IE
bit 21
INT3IE
bit 21
Bit 5
—
—
—
(1)
Top-of-Stack Upper Byte (TOS<20:16>)
Holding Register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INTEDG2
INT0IE
INT2IE
Bit 4
SP4
—
Indirect Data Memory Address Pointer 0 High Byte
INTEDG3
INT1IE
RBIE
Bit 3
SP3
PIC18F46J11 FAMILY
• PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The Parallel Master Port (PMP)
module’s operating mode determines what func-
tion the registers take on. See Section 10.1.2
“Data Registers” for additional details.
TMR0IF
TMR0IP
INT3IF
Bit 2
SP2
2
C™ Slave mode. See Section 18.5.3.2 “Address
INT3IP
INT0IF
INT2IF
Bit 1
SP1
INT1IF
RBIF
RBIP
Bit 0
SP0
DS39932C-page 83
---0 0000 63, 75
0000 0000 63, 73
0000 0000 63, 73
00-0 0000 63, 74
---0 0000 63, 73
0000 0000 63, 73
0000 0000 63, 73
--00 0000 63, 106
0000 0000 63, 106
0000 0000 63, 106
0000 0000 63, 106
xxxx xxxx 63, 63
xxxx xxxx 63, 107
0000 000x 63, 111
1111 1111 63, 112
1100 0000 63, 113
---- xxxx 63, 91
xxxx xxxx 63, 91
xxxx xxxx 63, 75
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Details
Page:
63, 91
63, 92
63, 92
63, 92
63, 92
63, 91
63, 92
63, 92
63, 92
63, 92
on
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