PIC18F26J11-I/SO Microchip Technology, PIC18F26J11-I/SO Datasheet - Page 237
![IC PIC MCU FLASH 64K 2V 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F26J11-I/SO
Manufacturer Part Number
PIC18F26J11-I/SO
Description
IC PIC MCU FLASH 64K 2V 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F26J11-I/SO
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 237 of 528
- Download datasheet (8Mb)
16.3
The alarm features and characteristics are:
• Configurable from half a second to one year
• Enabled using the ALRMEN bit (ALRMCFG<7>,
• Offers one-time and repeat alarm options
16.3.1
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. The bit will
not be cleared if the CHIME bit = 1 or if ALRMRPT ≠ 0.
The interval selection of the alarm is configured
through the ALRMCFG bits (AMASK<3:0>). (See
Figure 16-5.) These bits determine which and how
many digits of the alarm must match the clock value for
the alarm to occur.
FIGURE 16-5:
© 2009 Microchip Technology Inc.
Register 16-4)
Note 1:
0000 – Every half second
0001 – Every second
0010 – Every 10 seconds
0011 – Every minute
0100 – Every 10 minutes
0101 – Every hour
0110 – Every day
0111 – Every week
1000 – Every month
1001 – Every year
Alarm Mask Setting
Alarm
AMASK<3:0>
CONFIGURING THE ALARM
Annually, except when configured for February 29.
ALARM MASK SETTINGS
(1)
Day of the
Week
d
Month
m
m
PIC18F46J11 FAMILY
The alarm can also be configured to repeat based on a
preconfigured interval. The number of times this occurs
after the alarm is enabled is stored in the ALRMRPT
register.
Note:
d
d
Day
d
d
While the alarm is enabled (ALRMEN = 1),
changing any of the registers – other than
the RTCCAL, ALRMCFG and ALRMRPT
registers and the CHIME bit – can result in
a false alarm event leading to a false
alarm interrupt. To avoid this, only change
the timer and alarm values while the alarm
is disabled (ALRMEN = 0). It is recom-
mended
ALRMRPT registers and CHIME bit be
changed when RTCSYNC = 0.
Hours
h
h
h
h
h
h
h
h
that
Minutes
m
m
m
m
m
the
m
m
m
m
m
m
DS39932C-page 237
ALRMCFG
Seconds
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
and
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