PIC18F26J11-I/SO Microchip Technology, PIC18F26J11-I/SO Datasheet - Page 108
![IC PIC MCU FLASH 64K 2V 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F26J11-I/SO
Manufacturer Part Number
PIC18F26J11-I/SO
Description
IC PIC MCU FLASH 64K 2V 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18F26J11-I/SO
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180023, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- MA180023 PDF datasheet
- PIC18LF24J10-ISS PDF datasheet #2
- PIC18F24J11-ISS PDF datasheet #3
- PIC18F26J11-ISO PDF datasheet #4
- Current page: 108 of 528
- Download datasheet (8Mb)
PIC18F46J11 FAMILY
Example 7-3 provides the instruction sequence for a
16 x 16 unsigned multiplication. Equation 7-1 provides
the algorithm that is used. The 32-bit result is stored in
four registers (RES<3:0>).
EQUATION 7-1:
EXAMPLE 7-3:
Example 7-4 provides the sequence to do a 16 x 16
signed multiply. Equation 7-2 provides the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
DS39932C-page 108
RES3:RES0
;
;
;
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
=
=
ARG1L, W
ARG2L
PRODH, RES1
PRODL, RES0
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
ARG1L, W
ARG2H
PRODL, W
RES1, F
PRODH, W
WREG
ARG1H, W
ARG2L
PRODL, W
RES1, F
PRODH, W
WREG
ARG1H:ARG1L · ARG2H:ARG2L
(ARG1H · ARG2H · 2
(ARG1H · ARG2L · 2
(ARG1L · ARG2H · 2
(ARG1L · ARG2L)
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
8
8
16
) +
) +
) +
EQUATION 7-2:
EXAMPLE 7-4:
RES3:RES0
;
;
;
;
;
SIGN_ARG1
;
CONT_CODE
:
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF
ADDWFC RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB RES3
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB RES3
=
=
ARG1L, W
ARG2L
PRODH, RES1
PRODL, RES0
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
ARG1L, W
ARG2H
PRODL, W
RES1, F
PRODH, W
WREG
ARG1H, W
ARG2L
PRODL, W
RES1, F
PRODH, W
WREG
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
ARG1H:ARG1L · ARG2H:ARG2L
(ARG1H · ARG2H · 2
(ARG1H · ARG2L · 2
(ARG1L · ARG2H · 2
(ARG1L · ARG2L) +
(-1 · ARG2H<7> · ARG1H:ARG1L · 2
(-1 · ARG1H<7> · ARG2H:ARG2L · 2
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
16 x 16 SIGNED MULTIPLY
ROUTINE
© 2009 Microchip Technology Inc.
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
; ARG1H:ARG1L neg?
; no, done
;
;
;
8
8
16
) +
) +
) +
16
16
) +
)
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