PIC16F648A-I/ML Microchip Technology, PIC16F648A-I/ML Datasheet - Page 84

• Manufacturer Part Number: PIC16F648A-I/ML
• Description: IC MCU FLASH 4KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F648A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F627A/628A/648A
Follow these steps when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If an OERR error occurred, clear the error by
TABLE 12-7:
DS40044D-page 82
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
clearing enable bit CREN.
PIR1
RCSTA
RCREG USART Receive Data Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
Name
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
SPEN
CSRC
Bit 7
EEIF
EEIE
CMIF
CMIE
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIF
Bit 5
CREN
SYNC
TXIE
Bit 4
TXIF
ADEN
Bit 3
—
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
BRGH
FERR
Bit 2
OERR
TRMT
Bit 1
RX9D
TX9D
Bit 0
© 2005 Microchip Technology Inc.
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
Value on
POR
Value on
all other
Resets