PIC16F648A-I/ML Microchip Technology, PIC16F648A-I/ML Datasheet - Page 60
![IC MCU FLASH 4KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F648A-I/ML
Manufacturer Part Number
PIC16F648A-I/ML
Description
IC MCU FLASH 4KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
5.PIC16F627A-IML.pdf
(180 pages)
Specifications of PIC16F648A-I/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
No.
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F627A-IP PDF datasheet #2
- PIC16F627A-IP PDF datasheet #3
- PIC16F627A-IP PDF datasheet #4
- PIC16F627A-IML PDF datasheet #5
- Current page: 60 of 180
- Download datasheet (3Mb)
PIC16F627A/628A/648A
9.3
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
pin an output.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3 “Set-
Up for PWM Operation”.
FIGURE 9-3:
DS40044D-page 58
Note
Note:
CCPR1L
CCPR1H (Slave)
Comparator
Duty cycle registers
PR2
TMR2
1:
Comparator
PWM Mode
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time base.
(1)
Clear Timer,
CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
R
S
Q
TRISB<3>
RB3/CCP1
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(frequency = 1/period).
FIGURE 9-4:
9.3.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
PWM period
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
Note:
TMR2 = PR2
Duty Cycle
PWM PERIOD
The Timer2 postscaler (see Section 8.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
=
Period
PR2
TMR2 = Duty Cycle
PWM OUTPUT
© 2005 Microchip Technology Inc.
+
1
TMR2 = PR2
4
Tosc TMR2 prescale
value
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