PIC18F24J11-I/SP Microchip Technology, PIC18F24J11-I/SP Datasheet - Page 53
![IC PIC MCU FLASH 16KB 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F24J11-I/SP
Manufacturer Part Number
PIC18F24J11-I/SP
Description
IC PIC MCU FLASH 16KB 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F24J11-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 53 of 528
- Download datasheet (8Mb)
REGISTER 3-3:
REGISTER 3-4:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
All register bits are maintained unless: V
Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
All register bits are maintained unless: V
Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1
(BANKED F4Fh)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
Deep Sleep Persistent General Purpose bits
Deep Sleep Persistent General Purpose bits
DDCORE
DDCORE
R/W-xxxx
R/W-xxxx
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
drops below the normal BOR threshold outside of Deep
drops below the normal BOR threshold outside of Deep
PIC18F46J11 FAMILY
(1)
(1)
DD
DD
is hard cycled to near V
is hard cycled to near V
x = Bit is unknown
x = Bit is unknown
DD
DD
drops below the
drops below the
SS
SS
DS39932C-page 53
.
.
bit 0
bit 0
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