PIC18F24J11-I/SP Microchip Technology, PIC18F24J11-I/SP Datasheet - Page 476
![IC PIC MCU FLASH 16KB 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F24J11-I/SP
Manufacturer Part Number
PIC18F24J11-I/SP
Description
IC PIC MCU FLASH 16KB 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F24J11-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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PIC18F46J11 FAMILY
TABLE 28-1:
TABLE 28-2:
TABLE 28-3:
DS39932C-page 476
DC CHARACTERISTICS
D100
D130
D131
D132B V
D133A T
D133B T
D134
D135
Operating Conditions: 3.0V < V
D300
D301
D302
300
301
Note 1:
Param
DC CHARACTERISTICS
Note 1:
Param
Param
No.
No.
No.
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only
I
E
V
T
I
ULP
DDP
Sym
I
I
I
IW
IE
RETD
V
V
V
CMRR
T
T
OUT
OUT
OUT
P
PR
PEW
Sym
RESP
MC
IOFF
ICM
IRV
and are not tested.
Sym
Response time measured with one comparator input at V
Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).
1
2
3
2
OV
Ultra Low-Power Wake-up Current
Program Flash Memory
Cell Endurance
V
V
Write
Self-Timed Write Cycle Time
Self-Timed Block Erase Cycle Time
Characteristic Retention
Supply Current during Programming
CTMU Current Source, Base Range
CTMU Current Source, 10x Range
CTMU Current Source, 100x Range
DD
DDCORE
MEMORY PROGRAMMING REQUIREMENTS
COMPARATOR SPECIFICATIONS
CTMU CURRENT SOURCE SPECIFICATIONS
Input Offset Voltage
Input Common Mode Voltage
Internal Reference Voltage
Common Mode Rejection Ratio
Response Time
Comparator Mode Change to Output Valid
core for Read
for Self-Timed Erase or
Characteristic
Characteristic
DD
Characteristics
(1)
< 3.6V, -40°C < T
A
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ T
V
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
2.25
Min
10K
< +85°C (unless otherwise stated)
20
—
—
—
—
MIN
Min
—
—
—
Typ†
33.0
2.8
60
—
—
—
—
3
Typ
550
5.5
DD
55
0.57
Min
—
55
—
—
0
(1)
/2, while the other input transitions from V
Max
2.75
2.75
—
—
—
—
—
—
0.60
Typ
150
Max
±5
—
—
—
—
—
—
Units
Year Provided no other specifications are
E/W
mA
-40°C ≤ T
ms
ms
nA
V
V
Max
0.63
V
±25
400
Net of I/O leakage and current
sink at 1.6V on pin,
V
See Application Note AN879,
“Using the Microchip Ultra
Low-Power Wake-up Module”
(DS00879)
-40°C to +85°C
V
64 bytes
violated
Units
A
10
—
DD
nA
μA
μA
DD
MIN
≤ +85°C for industrial
A
© 2009 Microchip Technology Inc.
≤ +85°C for Industrial
= 3.3V
= Minimum operating voltage
CTMUICON<1:0> = 01
CTMUICON<1:0> = 10
CTMUICON<1:0> = 11
Units
mV
dB
ns
μs
V
V
Conditions
Conditions
Comments
SS
to V
DD
.
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