PIC16F1937-I/ML Microchip Technology, PIC16F1937-I/ML Datasheet - Page 374

• Manufacturer Part Number: PIC16F1937-I/ML
• Description: IC PIC MCU FLASH 512KX14 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/ML

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F193X/LF193X
MOVIW
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41364D-page 374
mm
00
01
10
11
Move literal to BSR
[ label ] MOVLB k
0  k  15
k  BSR
None
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
Move INDFn to W
[ label ] MOVIW ++INDFn
[ label ] MOVIW --INDFn
[ label ] MOVIW INDFn++
[ label ] MOVIW INDFn--
[ label ] MOVIW k[INDFn]
[ label ] MOVIW INDFn
n  [0,1]
mm  [00, 01, 10, 11].
-32  k  31
If not present, k = 0.
INDFn  W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
Z
Mode
Preincrement
Predecrement
Postincrement
Postdecrement
Syntax
++INDFn
--INDFn
INDFn++
INDFn--
Preliminary
MOVLP
Syntax:
Operands:
Operation:
Status Affected:
Description:
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
Cycles:
Example:
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
Cycles:
Example:
Move literal to W
[ label ]
0  k  255
k  (W)
None
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assem-
ble as ‘0’s.
1
1
After Instruction
Move literal to PCLATH
[ label ] MOVLP k
0  k  127
k  PCLATH
None
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
Move W to f
[ label ]
0  f  127
(W)  (f)
None
Move data from W register to register
‘f’.
1
1
Before Instruction
After Instruction
MOVLW
MOVWF
 2009 Microchip Technology Inc.
MOVLW k
W
MOVWF
OPTION =
W
OPTION =
W
0x5A
OPTION
=
0x5A
=
=
f
0xFF
0x4F
0x4F
0x4F