PIC16F1937-I/ML Microchip Technology, PIC16F1937-I/ML Datasheet - Page 355

• Manufacturer Part Number: PIC16F1937-I/ML
• Description: IC PIC MCU FLASH 512KX14 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/ML

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.10 LCD Interrupts
The LCD module provides an interrupt in two cases. An
interrupt when the LCD controller goes from active to
inactive controller. An interrupt also provides unframe
boundaries for Type B waveform. The LCD timing gen-
eration provides an interrupt that defines the LCD
frame timing.
26.10.1
An LCD interrupt is generated when the module com-
pletes shutting down (LCDA goes from ‘1’ to ‘0’).
26.10.2
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes access-
ing all pixel data required for a frame. This will occur at
a fixed interval before the frame boundary (T
shown in Figure 26-19. The LCD controller will begin to
access data for the next frame within the interval from
the interrupt to when the controller begins to access
data after the interrupt (T
ten within T
begin to access the data for the next frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’ (static
drive), there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
were allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel.
Therefore, when using Type-B waveforms, the user
must synchronize the LCD pixel updates to occur within
a subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR bit of the LCDCON register is set and the
write does not occur.
 2009 Microchip Technology Inc.
Note:
The LCD frame interrupt is not generated
when the Type-A waveform is selected and
when the Type-B with no multiplex (static)
is selected.
FWR
LCD INTERRUPT ON MODULE
SHUTDOWN
LCD FRAME INTERRUPTS
, as this is when the LCD controller will
FWR
). New data must be writ-
FINT
), as
Preliminary
PIC16F193X/LF193X
DS41364D-page 355