PIC16F1937-I/ML Microchip Technology, PIC16F1937-I/ML Datasheet - Page 315

• Manufacturer Part Number: PIC16F1937-I/ML
• Description: IC PIC MCU FLASH 512KX14 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/ML

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 24.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
 2009 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave
never Idle
Name
*
Reception.
Page provides register information.
EUSART Synchronous Slave
Reception
EUSART Receive Data Register
TMR1GIE
TMR1GIF
ABDOVF
TRISC7
CSRC
SPEN
Bit 7
RECEPTION
GIE
TRISC6
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
TRISC4
Preliminary
CREN
SCKP
SYNC
INTE
Bit 4
TXIE
TXIF
TRISC3
ADDEN
SENDB
BRG16
SSPIE
SSPIF
IOCIE
24.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 3
PIC16F193X/LF193X
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IE
CCP1IF
TRISC2
BRGH
FERR
Bit 2
—
Synchronous Slave Reception
Set-up:
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
WUE
Bit 1
INTF
TMR1IE
TMR1IF
TRISC0
ABDEN
IOCIF
RX9D
TX9D
Bit 0
DS41364D-page 315
Register
on Page
294*
300
100
103
299
140
298
99