PIC16F1938-I/ML Microchip Technology, PIC16F1938-I/ML Datasheet - Page 290

• Manufacturer Part Number: PIC16F1938-I/ML
• Description: IC MCU 8BIT FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1938-I/ML

• Core Size: 8-Bit
• Program Memory Size: 28KB (16K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 32MHz
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F193X/LF193X
22.4.4
The I
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 22-8 shows wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I
states no bus collision can occur on a Start.
22.4.5
A Stop condition is a transition of the SDA line from
low to high state while the SCL line is high.
FIGURE 22-9:
DS41364C-page 290
Note: The Philips I
Note: At least one SCL low time must appear
2
C specification defines a Start condition as a
START CONDITION
STOP CONDITION
bus collision cannot occur on a Start, and
should occur during the address sequence.
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
SDA
SCL
I
2
2
C Specification states that a
C START AND STOP CONDITIONS
Condition
Start
S
2
C Specification that
Data Allowed
Change of
Preliminary
22.4.6
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully address, matching
both high and low address bytes, the master can issue
a Restart and the high address byte with the R/W bit
set. The slave logic will then hold the clock and pre-
pare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
22.4.7
The SCIE and PCIE bits of the SSPCON3 register can
enable the generation of an interrupt in Slave mode.
Slave modes where interrupt on Start and Stop detect
are already enabled, these bits will have no effect.
Data Allowed
RESTART CONDITION
START/STOP CONDITION INTERRUPT
MASKING
Change of
© 2009 Microchip Technology Inc.
Condition
Stop
P