PIC12F519-I/SN Microchip Technology, PIC12F519-I/SN Datasheet - Page 25

• Manufacturer Part Number: PIC12F519-I/SN
• Description: IC PIC MCU FLASH 1KX12 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F519-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.5KB (1K x 12)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Interface Type: USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• Height: 1.25 mm
• Length: 4.9 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 3.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
6.1
GPIO is an 8-bit I/O register. Only the low-order 6 bits
are used (GP<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s. Please note that GP3 is an input-only
pin. The Configuration Word can set several I/O’s to
alternate functions. When acting as alternate functions,
the pins will read as ‘0’ during a port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also for wake-up on change. The wake-up on
change and weak pull-up functions are not pin select-
able. If GP3/MCLR is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not enabled.
TABLE 6-1:
© 2008 Microchip Technology Inc.
Note 1: When MCLRE = 1, the weak pull-up on GP3/MCLR is always
2:
I/O PORT
GPIO
enabled.
GP0
GP1
GP2
GP3
GP4
GP5
GP6
WPU = Weak pull-up; WU = Wake-up.
Pin
WEAK PULL-UP ENABLED PINS
WPU
Y
N
N
N
N
Y
Y
(1)
WU
Y
Y
N
Y
N
N
N
6.2
The Output Driver Control registers are loaded with
the contents of the W Register by executing the TRIS
f instruction. A ‘1’ from a TRISGPIO Register bit puts
the corresponding output driver in a high-impedance
(Input) mode. A ‘0’ puts the contents of the output data
latch on the selected pins, enabling the output buffer.
The TRISGPIO register is “write-only”. Bits <5:0> are
set (output drivers disabled) upon Reset.
Note:
TRIS Registers
If the T0CS bit is set to ‘1’, it will override
the TRISGPIO function on the T0CKI pin.
PIC12F519
DS41319B-page 23