MPC8349E-MDS-PBE Freescale Semiconductor, MPC8349E-MDS-PBE Datasheet - Page 4

• Manufacturer Part Number: MPC8349E-MDS-PBE
• Description: KIT MODULAR DEV SYSTEM MPC8349E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8349E-MDS-PBE

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switches: SW3 Configuration Set 1
Switches: SW4 Configuration Set 2
Switches: SW6 Configuration Set 3
Note! A DIP-switch in the ON position
creates a zero-value signal.
4
1: TSEC1-0
2: TSEC1-1
3: TSEC2-0
4: TSEC2-1
5: BMS
6: TLE
7: PCI64
8: FCFG
1: BOOT SEQ0
2: BOOT SEQ1
3: ROMLOC0
4: ROMLOC1
5: ROMLOC2
6: DDRCM
7: LBIUCM
8: SWEN
1: CFG_RS0
2: CFG_RS1
3: CFG_RS2
4: CLKDIV
5: SPMF0
6: SPMF1
7: SPMF2
8: SPMF3
1 <-> 0
1 <-> 0
1 <-> 0
MPC8349E MDS Processor Board HW Getting Started Guide
SW3.1-SW3.3
SW3.5-SW3.8
SW4.1,2-SW4.3,4: TSEC1/TSEC2
SW4.5 BMS: Selects boot memory space
SW4.6 TLE: Selects endian mode
SW4.7 PCI64: Selects PCI width
SW4.8 FCFG: Sets RCW source on local bus
SW6.1-SW6.2: Boot sequencer configuration
SW6.3-SW6.5: Boot ROM location
SW6.6 DDR: Clock mode
SW6.7: Local bus clock mode
SW6.8: Software watchdog
SW3.4
• CFG_RS sets the RCW source.
• ON: value of zero.
• Factory setting: ‘000' when RCW fetched from the local bus.
• DIP-switch SW4.8 FCFG: chooses between BCSR or Flash
• CLKDIV selects the relationship between CLKIN and
• If the MPC8349E MDS processor board is configured as a PCI
• SPMF: select System PLL Multiplication Factor.
• Factory setting: ‘0100’.
• Clock ratio: csb_clk/CLKIN = 4 (csb_clk = 266MHz) or
• Select the protocol used by the two port TSEC controller.
• Factory setting: enters GMII mode when TSEC1 and TSEC2
• Factory setting is ‘1' when boot memory resides in upper eight
• Factory setting: ‘0'; big endian mode.
• 32-bit PCI port factory setting: ‘0'.
• ‘0': BCSR source; setting is effective from DIP-switches SW3-
• ‘1’: Flash source—setting is burned in flash.
• Factory setting: ‘1'; configured from flash.
• Boot sequencer loads configuration data from the serial ROM.
• Factory setting: ‘00'; disables access to I2C ROM.
• Factory setting: ‘110'; provides flash boot on local bus.
• Factory setting: ‘0'; with software watchdog disabled.
RCW source.
PCI_SYNC_OUT.
Agent (factory setting) then CLKDIV is set to zero.
csb_clk/PCI_CLK = 4.
initiate similar 2’b10.
Mbytes at 0xFF80_0000 to 0xFFFF_FFFF.
SW6.
•
•
Factory setting: ‘0'; operates with DDR clock
(identical to csb_clk).
Factory setting: ‘1'; operates with local bus
clock—half of csb_clk.