MT16VDDF12864HG-40BF2 Micron Technology Inc, MT16VDDF12864HG-40BF2 Datasheet - Page 5

• Manufacturer Part Number: MT16VDDF12864HG-40BF2
• Description: MODULE DDR SDRAM 1GB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDF12864HG-40BF2

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.6A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
PDF: 09005aef80a77a90/Source: 09005aef80a646bc
DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN
DQS0–DQS7
CKE0, CKE1
WE#, CAS#,
DQ0–DQ63
CK0, CK0#,
DM0–DM7
CK1, CK1#
BA0, BA1
SA0–SA2
Symbol
S0#, S1#
A0–A12
V
RAS#
SDA
DDSPD
V
V
SCL
V
NC
NF
REF
DD
SS
Pin Descriptions
Output
Output
Output
Supply
Supply
Supply
Supply
Input/
Input/
Input/
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
–
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-
code during a MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
Clock: CK, CK# are differential clock inputs. All control, command, and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output
data (DQ and DQS) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates the
internal clock, input buffers, and output drivers.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Presence-detect address inputs: These pins are used to configure the SPD EEPROM address
range on the I
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data
into and out of the presence-detect portion of the module.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH, along with that input data, during a write access. DM is sampled on both
edges of DQS. Although the DM pins are input-only, the DM loading is designed to match
that of DQ and DQS pins.
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data. Used to capture data.
Power supply: +2.5V ±0.2V.
Serial EEPROM positive power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
No function: These pins are connected within the module, but provide no functionality.
2
C bus.
DD
/2).
5
512MB, 1GB (x64, DR) 200-Pin DDR SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2003 Micron Technology, Inc. All rights reserved