MT16VDDF12864HG-40BF2 Micron Technology Inc, MT16VDDF12864HG-40BF2 Datasheet - Page 11

• Manufacturer Part Number: MT16VDDF12864HG-40BF2
• Description: MODULE DDR SDRAM 1GB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDF12864HG-40BF2

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.6A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 10:
PDF: 09005aef80a77a90/Source: 09005aef80a646bc
DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN
Parameter/Condition
Operating one bank active-precharge current: One
device bank; Active-precharge
(MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two
clock cycles
Operating one bank active-read-precharge current: One
device bank; Active-read-precharge; BL = 4;
t
changing once per clock cycle
Precharge power-down standby current: All device banks
idle; Power-down mode;
Idle standby current: CS# = HIGH; All device banks are idle;
t
inputs changing once per clock cycle. V
and DM
Active power-down standby current: One device bank
active; Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank active;
DM, and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle;
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle;
DQS inputs changing twice per clock cycle
Auto refresh burst current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device
bank interleaving READs (BL = 4) with auto precharge;
t
control inputs change only during active READ or WRITE
commands
CK =
CK =
RC = (MIN)
t
t
CK (MIN); I
CK (MIN); CKE = HIGH; Address and other control
t
RC allowed;
I
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
DD
OUT
Specifications and Conditions – 512MB (All Other Die Revisions)
Notes:
t
RC =
= 0mA; Address and control inputs
t
t
t
CK =
CK = tCK (MIN); CKE = (LOW)
RAS (MAX);
t
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
3. The standard module guarantees I
CK =
;
t
t
t
in I
t
CK =
CK =
CK (MIN); Address and
RC
t
CK (MIN); CKE = LOW
DD
=
2P (CKE LOW) mode.
t
t
t
CK (MIN); I
CK (MIN); DQ, DM, and
RC (MIN);
t
IN
CK =
= V
t
t
Standard
Low power
REFC =
REFC = 7.8125µs
t
t
REF
RC =
CK (MIN); DQ,
for DQ, DQS,
OUT
t
CK =
t
t
RC (MIN);
RFC (MIN)
= 0mA
t
CK
11
512MB, 1GB (x64, DR) 200-Pin DDR SODIMM
I
Symbol
I
DD
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
DD
DD
6A
4W
6
3N
4R
5A
2P
2F
3P
6 and the low power module guarantees I
0
1
5
7
2, 3
2, 3
1
1
2
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
2
2
1
2
2
1
1,112
1,392
1,120
1,632
1,592
4,160
3,792
-40B
960
640
64
96
64
32
Electrical Specifications
1,032
1,392
1,432
1,432
4,080
3,312
-335
800
480
960
64
96
64
32
©2003 Micron Technology, Inc. All rights reserved
1,192
1,232
1,232
3,920
2,952
-265
992
720
480
800
64
96
64
32
DD
6A.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA