MT16LSDT3264AG-13EG3 Micron Technology Inc, MT16LSDT3264AG-13EG3 Datasheet - Page 10

• Manufacturer Part Number: MT16LSDT3264AG-13EG3
• Description: MODULE SDRAM 256MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDT3264AG-13EG3

• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 7:
NOTE:
operation or incompatibility with future versions may
result.
09005aef80bccbe7
SD8_16C16_32x64AG.fm - Rev. E 12/05 EN
Full Page
LENGTH
1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1–A9 select the block-of-
3. For a burst length of four,A2–A9 select the block-of-
4. For a burst length of eight, A3–A9 select the block-of-
5. For a full-page burst, the full row is selected and A0–A9
6. Whenever a boundary of the block is reached within a
7. For a burst length of one, A0–A9 select the unique col-
BURST
Reserved states should not be used as unknown
two burst; A0 selects the starting column within the
block.
four burst; A0–A1 select the starting column within the
block.
eight burst; A0–A2 select the starting column within
the block.
select the starting column.
given sequence above, the following access wraps
within the block.
umn to be accessed, and mode register bit M3 is
ignored.
(y)
2
4
8
A2 A1 A0
(location 0-y)
0
0
0
0
1
1
1
1
STARTING
n = A0–A9
COLUMN
Burst Definition
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Cn + 2, Cn + 3,
…Cn - 1, Cn…
SEQUENTIAL
Cn, Cn + 1,
Cn + 4...
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
A BURST ADDRESS
0-1
1-0
INTERLEAVED
Not Supported
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
10
128MB (x64, SR), 256MB (x64, DR)
CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a read command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in the CAS Latency Dia-
gram. The CAS Latency Table indicates the operating
frequencies at which each CAS latency setting can be
used.
Operating Mode
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
read and write bursts.
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
The normal operating mode is selected by setting
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 6: CAS Latency Diagram
READ
READ
T0
T0
168-PIN SDRAM UDIMM
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
©2003, 2004 Micron Technology, Inc. All rights reserved.
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4