MT9LSDT1672AY-133G3 Micron Technology Inc, MT9LSDT1672AY-133G3 Datasheet - Page 8

• Manufacturer Part Number: MT9LSDT1672AY-133G3
• Description: MODULE SDRAM 128MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9LSDT1672AY-133G3

• Memory Type: SDRAM
• Memory Size: 128MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 72b
• Organization: 16Mx72
• Total Density: 128MByte
• Chip Density: 128Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.35A
• Number Of Elements: 9
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
are high-speed CMOS, dynamic random-access,
128MB and 256MB DIMMs organized in a x72 (ECC)
configuration. SDRAM modules use internally config-
ured quad-bank SDRAM devices with a synchronous
interface (all signals are registered on the positive edge
of the clock signals).
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the device bank and row to be accessed (BA0,
BA1 select the device bank, A0–A11 select the device
row). The address bits registered coincident with the
READ or WRITE command are used to select the start-
ing column location for the burst access.
or WRITE burst lengths of 1, 2, 4, or 8 locations, or the
full page, with a burst terminate option. An AUTO PRE-
CHARGE function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence.
ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
DRAM operating performance, including the ability to
syn-chronously burst data at a high data rate with
automatic column-address generation, the ability to
interleave between internal device banks in order to
hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access. For more information regarding SDRAM
operation, refer to the 128Mb SDRAM component data
sheet.
Serial Presence-Detect Operation
(SPD). The SPD function is implemented using a
09005aef807b3709
SD9_18C16_32x72AG.fm - Rev. E 6/04 EN
The MT9LSDT1672 and MT18LSDT3272A modules
Read and write accesses to the SDRAM modules are
SDRAM modules provide for programmable READ
SDRAM modules use an internal pipelined architec-
SDRAM modules are designed to operate in 3.3V,
SDRAM modules offer substantial advances in
These modules incorporate serial presence-detect
128MB (x72, ECC, SR), 256MB (x72, ECC, DR)
8
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP . Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Mode Register Definition
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 5, Mode Register Definition
Diagram, on page 9. The mode register is programmed
via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed
again or the device loses power.
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
SDRAMs must be powered up and initialized in a
Once the 100µs delay has been satisfied with at least
Once in the idle state, two AUTO REFRESH cycles
The mode register is used to define the specific
Mode register bits M0–M2 specify the burst length,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM UDIMM
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and V
©2004 Micron Technology, Inc.
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