MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 11

• Manufacturer Part Number: MT4VDDT3264HY-335F2
• Description: MODULE DDR 256MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 780mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1231; MT4VDDT3264HY-335F2

mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power.
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
Output Drive Strength
specified to be SSTL2, Class II. The reduced drive
option is intended for the support of the lighter load
and/or point-to-point environments.
reduced drive strength option, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data
sheets.
DLL Enable/Disable
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
a DLL Reset and 200 clock cycles with CKE HIGH must
occur before a READ command can be issued.
pdf: 09005aef8086ea3d, source: 09005aef8086ea0b
DD4C8_16_32x64HG.fm - Rev. C 9/04 EN
The extended mode register must be loaded when
The normal full drive strength for all outputs is
For detailed information on programmable and
The DLL must be enabled for normal operation.
The
11
NOTE:
128MB, 256MB Modules
64MB Module
E11
1. BA1 and BA0 (E13 and E12 for 64MB, E14 and E13 for
2. QFC# is not supported.
0
14
0
–
BA1 BA0
64MB, 128MB, 256MB (x64, SR)
1
128MB, 256MB) must be “0, 1” to select the Extended
Mode Register (vs. the base Mode Register).
Figure 7: Extended Mode Register
E10
200-PIN DDR SDRAM SODIMM
1
0
13
0
–
BA1 BA0
13
1
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
E9
12
0
–
12
A12
1
E8
11
11
0
–
A11
A11
E7
0
–
10
10
A10
A10
Definition Diagram
E6 E5
0
–
9
9
Operating Mode
A9
A9
Operating Mode
0
–
8
8
A8
A8
E4
0
–
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
E3
0
–
6
6
E2
0
–
2
5
5
©2004 Micron Technology, Inc. All rights reserved.
4
4
E1,
Valid
–
3
E0
3
2
2
A2 A1 A0
A2 A1 A0
DS
Operating Mode
Normal Operation
All other states reserved
DS
1
1
E1
0
1
DLL
DLL
0
0
E0
0
1
Extended Mode
Register (Ex)
Drive Strength
Extended Mode
Register (Ex)
Address Bus
Address Bus
Reduced
Disable
Normal
Enable
DLL