IDT72V51246L7-5BB IDT, Integrated Device Technology Inc, IDT72V51246L7-5BB Datasheet - Page 9

• Manufacturer Part Number: IDT72V51246L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51246L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51246L7-5BB

PIN DESCRIPTIONS (CONTINUED)
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
OW
PAE
PAEn/PRn
PAF
PAFn
PKT
PR
PRS
Symbol
(1)
(1)
Output Width
Programmable
Almost-Empty Flag
Programmable
Almost-Empty Flag
Bus/Packet Ready
Flag Bus
Programmable
Almost-Full Flag
Programmable
Almost-Full Flag Bus OUTPUT a selected device. During Queue read/write operations these outputs provide programmable full flag
Packet Mode
Packet Ready Flag
Partial Reset
Name
I/O TYPE
OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
OUTPUT Almost Empty mode or Packet mode. This output bus provides PAE/ PRn status of all 4 queues, within
OUTPUT write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue
LVTTL
INPUT
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
INPUT
LVTTL
LVTTL
INPUT
If packet mode has been selected this flag output provides Packet Ready status of the queue selected
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9,
x18 or x36, (providing that one port is x36).
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
On the 4Q device the PAEn/ PRn bus is 4 bits wide. During a Master Reset this bus is setup for either
a selected device. During Queue read/write operations these outputs provide programmable empty
during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this
is important during expansion of multi-queue devices. During direct operation the PAEn/ PRn bus is
updated to show the PAE/PR status of queues within a selected device. Selection is made using RCLK,
ESTR and RDADD. During Polled operation the PAEn/ PRn bus is loaded with the PAE/ PRn status
of multi-queue flow-control devices sequentially based on the rising edge of RCLK. PAE or PR operation
is determined by the state of PKT during master reset.
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is synchronized
to WCLK.
On the 4Q device the PAFn bus is 4 bits wide. This output bus provides PAF status of all 4 queues, within
status, in either direct or polled mode. The mode of flag operation is determined during master reset
via the state of the FM input. This flag bus is capable of High-Impedance state, this is important during
expansion of multi-queue devices. During direct operation the PAFn bus is updated to show the PAF
status of a queues within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN.
During Polled operation the PAFn bus is loaded with the PAF status of multi-queue flow-control devices
sequentially based on the rising edge of WCLK.
The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output,
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read
port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional.
If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and
the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected. Packet
Ready utilizes user marked locations to identify start and end of packets being written into the device.
Packet Mode can only be selected if both the input port width and output port width are 36 bits.
for read operations. During a master reset the state of the PKT input determines whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the PR flag and OV signal are
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end
of a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet
(EOP) markers, the multi-queue device sets PR LOW if one or more “complete” packets are available
in the queue. A complete packet(s) must be written before the user is allowed to switch queues.
A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
flag status or packet ready status, in either director polled mode. The mode of flag operation is determined
9
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES