IDT72V51246L7-5BB IDT, Integrated Device Technology Inc, IDT72V51246L7-5BB Datasheet
IDT72V51246L7-5BB
Specifications of IDT72V51246L7-5BB
Related parts for IDT72V51246L7-5BB
IDT72V51246L7-5BB Summary of contents
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FEATURES: • • • • • Choose from among the following memory density options: IDT72V51236 Total Available Memory = 589,824 bits IDT72V51246 Total Available Memory = 1,179,648 bits ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DESCRIPTION: The IDT72V51236/72V51246/72V51256 multi-queue flow-control de- vices are single chip within which anywhere between 1 and 4 discrete FIFO queues can be setup. All ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK WEN 5 WRADD Write Control Logic WADEN Write Pointers PAF FSTR 4 General Flag PAFn Monitor FSYNC FXO FXI FF Active Q Flags ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN CONFIGURATION A1 BALL PAD CORNER A D14 D13 D12 D10 B D15 D16 D11 D9 C D17 D18 D19 D8 D D20 D21 ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DETAILED DESCRIPTION MULTI-QUEUE STRUCTURE The IDT multi-queue flow-control device has a single data input port and single data output port with ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits EXPANSION Expansion of multi-queue devices is also possible devices can be connected in a parallel fashion providing the possibility of both ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS Symbol Name I/O TYPE BM Bus Matching LVTTL INPUT D[35:0] Data Input Bus LVTTL Din INPUT (1) DF Default Flag LVTTL INPUT ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE PAFn Flag Bus FSTR LVTTL (Continued) Strobe INPUT PAFn Bus Sync FSYNC LVTTL OUTPUT during Polled operation ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE OW (1) Output Width LVTTL INPUT PAE Programmable LVTTL Almost-Empty Flag OUTPUT for read operations, (selected via ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE Q[35:0] Data Output Bus LVTTL OUTPUT of RCLK provided that REN is LOW LOW and ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE SENO Serial Output Enable LVTTL OUTPUT has been completed. SENO follows SENI once programming of a device ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O TYPE WEN Write Enable LVTTL INPUT WRADD Write Address Bus LVTTL [4:0] INPUT V +3.3V Supply Power CC ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1. ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC TEST LOADS Ω I/O Figure 2a. AC Test Load AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input ...
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... Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order. 2. Values guaranteed by design, not currently tested. = 3.3V ± 0.15V 40°C to +85°C; JEDEC JESD8-A compliant Commercial Com'l & Ind'l IDT72V51236L6 IDT72V51236L7-5 IDT72V51246L6 IDT72V51246L7-5 IDT72V51256L6 IDT72V51256L7-5 Min. Max. Min. — 166 — 0.6 3.7 ...
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... Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order. 2. Values guaranteed by design, not currently tested. = 3.3V ± 0.15V 40°C to +85°C; JEDEC JESD8-A compliant Commercial Com'l & Ind'l IDT72V51236L6 IDT72V51236L7-5 IDT72V51246L6 IDT72V51246L7-5 IDT72V51256L6 IDT72V51256L7-5 Min. Max. Min. 0.6 3.7 0.6 0.6 3.7 ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits FUNCTIONAL DESCRIPTION MASTER RESET A Master Reset is performed by toggling the MRS input from HIGH to LOW to HIGH. During a master reset ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits cycles are required for the device to load its internal setup registers. When a single multi-queue is used, the completion of device programming is ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits READ QUEUE SELECTION AND READ OPERATION (STANDARD MODE) The IDT72V51236/72V51346/72V51256 multi-queue flow-control de- vices can be configured maximum of 4 queues ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits (REOP). The minimum size for a packet is four words (SOP, two words of data and EOP). The almost empty flag bus becomes the ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 5 — PACKET MODE VALID BYTE TMOD1 (D33) RMOD1 (Q33) NOTE: Packet Mode is only available when the Input Port and Output Port ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits NULL QUEUE OPERATION (OF THE READ PORT) Pipelining of data to the output port enables the device to provide 100% bus utilization in standard ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits for the new queue one cycle ahead of the WCLK rising edge that data can be written into the new queue. That is, a ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits output to the PAF flag. This dedicated flag is often referred to as the “active queue almost full flag”. The position of the PAF ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING Output Valid, OV Flag Boundary I/O Set-Up OV Goes LOW after 1 In36 to out36 (Almost ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED) Programmable Almost Empty Flag, PAE Boundary I/O Set-Up in36 to out36 (Both ports selected for ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PAFn BUS EXPANSION - DIRECT MODE LOW at Master Reset then the PAFn bus operates in Direct (addressed) mode. In direct ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits MRS t RSS WEN REN t RSS SENI t RSS FSTR, ESTR t RSS WADEN, RADEN t RSS ID0, ID1, ID2 t RSS OW, ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits w-2 WCLK t QS WADEN WEN t AS WRADD Qx FF PAF Active Bus PAF-Qx (5) PRS RCLK REN t QS RADEN t AS ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 31 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 32 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 33 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK t ENS WEN RCLK REN Qout Last Word Read Out of Queue OV NOTES has ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 35 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 36 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK t ENS REN RDADD Addr=001011 RADEN Qout (Device 1) ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK t t ENS ENH REN t AS RDADD t QS RADEN OUT ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 39 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 40 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 41 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 42 TEMPERATURE RANGES ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits NULL QUEUE RCLK t AS RDADD t QS RADEN REN t A Qout Q1 Wn-3 Q1 Wn-2 OV NOTES: 1. The purpose of the ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* WCLK WEN WRADD WADEN Din PAF HIGH-Z (Device 1) PAF (Device ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK REN HIGH RDADD RADEN HIGH-Z Qout PAE HIGH-Z (Device ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* WCLK t QS WADEN FSTR t ENS WEN WRADD D5Q3 100 Writes to Previous Q RCLK t ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* RCLK t QS RADEN ESTR REN RDADD D0Q1 000 001 OE t OLZ Qout Prev. Q WCLK t STS FSTR ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK FSYNC 0 (MASTER) FXO 0 / FXI 1 FSYNC 1 (SLAVE) FXO 1 / FXI 2 FSYNC 2 (SLAVE) FXO 2 / FXI ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits RCLK ESYNC 0 EXO 0 / EXI 1 ESYNC 1 EXO 1 / FXI 2 ESYNC 2 EXO 2 / EXI 0 PAE n ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits Serial Programming Data Input Serial Enable Data Bus Write Clock Write Enable Write Queue Select Write Address Full Strobe Programmable Almost Full Full Sync1 ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V51236/72V51246/ 72V51256 incorporates ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and ...
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits t 1 TCK t 3 TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t DO ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order. DATASHEET DOCUMENT HISTORY 10/10/2001 pgs. 1, ...