IDT72V51246L7-5BB IDT, Integrated Device Technology Inc, IDT72V51246L7-5BB Datasheet - Page 26

• Manufacturer Part Number: IDT72V51246L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51246L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51246L7-5BB

PACKET READY FLAG, PR BOUNDARY
Assertion:
Both the rising and falling edges of PR are synchronous to RCLK.
PR Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assuming a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
From WCLK rising edge writing the TEOP word PR goes LOW after: t
+ 2 RCLK + t
If t
PR goes LOW after t
(Please refer to Figure 18, Data Input (Transmit) Packet Mode of Operation
for timing diagram).
De-assertion:
PR Rising Edge occurs upon reading the last RSOP marker, from output Q34.
i.e. there are no more complete packets available within the queue.
Timing:
From RCLK rising edge Reading the RSOP word the PR goes HIGH after:
2 RCLK + t
(Please refer to Figure 19, Data Output (Receive) Packet Mode of Operation
for timing diagram).
NOTE:
n = Almost Empty Offset value.
PAE Timing
Assertion:
De-assertion: Write to PAE HIGH: t
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
in36 to out36
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in36 to out18
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in36 to out9
(Both ports selected for same queue when the 1
in18 to out36
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in9 to out36
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
Word is written in until the boundary is reached)
SKEW4
is violated:
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Default values:
PR
Programmable Almost Empty Flag, PAE Boundary
Read Operation to PAE LOW: 2 RCLK + t
If t
PR
SKEW2
I/O Set-Up
SKEW4
is violated there may be 1 added clock: t
if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
+ 3 RCLK + t
SKEW2
+ RCLK + t
PR
st
st
st
st
st
RAE
(see note below for timing)
PAE Goes HIGH after n+2
Writes
(see note below for timing)
PAE Goes HIGH after n+1
Writes
(see note below for timing)
PAE Goes HIGH after n+1
Writes
PAE Goes HIGH after
([n+2] x 2) Writes
(see note below for timing)
PAE Goes HIGH after
([n+2] x 4) Writes
(see note below for timing)
RAE
PAE Assertion
SKEW2
+ 2 RCLK + t
SKEW4
RAE
26
NOTE:
n = Almost Empty Offset value.
PAEn Timing
Assertion:
De-assertion: Write to PAEn HIGH: t
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
PACKET READY FLAG BUS, PRn BOUNDARY
Assertion:
Both the rising and falling edges of PRn are synchronous to RCLK.
PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assuming a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
From WCLK rising edge writing the TEOP word PR goes LOW after: t
+ 2 RCLK* + t
If t
*If a queue switch is occurring on the read port at the point of flag assertion there
may be one additional RCLK clock cycle delay.
De-assertion:
PR Rising Edge occurs upon reading the last RSOP marker, from output Q34.
i.e. there are no more complete packets available within the queue.
Timing:
From RCLK rising edge Reading the RSOP word the PR goes HIGH after: 2
RCLK* + t
*If a queue switch is occurring on the read port at the point of flag assertion or
de-assertion there may be one additional RCLK clock cycle delay.
in36 to out36
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in36 to out36
(Write port only selected for same queue when the n+1 Writes
1
in36 to out18
in36 to out9
in18 to out36
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in18 to out36
(Write port only selected for same queue when the ([n+1] x 2) Writes
1
in9 to out36
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in9 to out36
(Write port only selected for same queue when the ([n+1] x 4) Writes
1
st
st
st
SKEW4
Word is written in until the boundary is reached) (see note below for timing)
Word is written in until the boundary is reached) (see note below for timing)
Word is written in until the boundary is reached) (see note below for timing)
Programmable Almost Empty Flag Bus, PAEn Boundary
is violated PRn goes LOW after t
PAE
Default values: if DF is LOW at Master Reset then n = 8
Read Operation to PAEn LOW: 2 RCLK* + t
If t
PAE
SKEW3
I/O Set-Up
is violated there may be 1 added clock: t
if DF is HIGH at Master Reset then n = 128
SKEW3
COMMERCIAL AND INDUSTRIAL
+ RCLK* + t
SKEW4
st
st
st
TEMPERATURE RANGES
PAEn Boundary Condition
PAEn Goes HIGH after
n+2 Writes
(see note below for timing)
PAEn Goes HIGH after
PAEn Goes HIGH after n+1
Writes (see below for timing)
PAEn Goes HIGH after n+1
PAEn Goes HIGH after
([n+2] x 2) Writes
(see note below for timing)
PAEn Goes HIGH after
PAEn Goes HIGH after
([n+2] x 4) Writes
(see note below for timing)
PAEn Goes HIGH after
Writes (see below for timing)
PAE
+ 3 RCLK* + t
PAE
SKEW3
+ 2 RCLK* + t
PAE
SKEW4
PAE