IDT72V51246L7-5BB IDT, Integrated Device Technology Inc, IDT72V51246L7-5BB Datasheet - Page 10

• Manufacturer Part Number: IDT72V51246L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51246L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51246L7-5BB

PIN DESCRIPTIONS (CONTINUED)
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Symbol
Q[35:0]
Qout
RADEN
RCLK
RDADD
[5:0]
REN
SCLK
SENI
Data Output Bus
Read Address
Enable
Read Clock
Read Address Bus
Read Enable
Serial Clock
Serial Input Enable
Name
I/O TYPE
OUTPUT of RCLK provided that REN is LOW, OE is LOW and the queue is selected. Note, that in Packet mode
LVTTL
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge
Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more detail.
Due to bus matching not all outputs may be used, any unused outputs should not be connected.
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part
has been completed and SENO has gone LOW.
When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
device to be placed on the PAEn/PRn bus during direct flag operation. During polled flag operation the
PAEn/PRn bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The PAE,
PR and OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals
are based on RCLK. RCLK must be continuous and free-running.
For the 4Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first
function of RDADD is to select a queue to be read from. The least significant 2 bits of the bus, RDADD[1:0]
are used to address 1 of 4 possible queues within a multi-queue device. Address pin, RDADD[2] provides
the user with a Null-Q address. If the user does not wish to address one of the 4 queues, a Null-Q can
be addressed using this pin. The Null-Q operation is discussed in more detail later. The most significant
3 bits, RDADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSb’s will address a device with the matching ID code. The address present
on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that
data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On
the next rising RCLK edge after a read queue select, a data word from the previous queue will be placed
onto the outputs, Qout, regardless of the REN input. Two RCLK rising edges after read queue select, data
will be placed on to the Qout outputs from the newly selected queue, regardless of REN due to the first
word fall through effect.
The second function of the RDADD bus is to select the device of queues to be loaded on to the PAEn/
PRn bus during strobed flag mode. The most significant 3 bits, RDADD[5:3] are again used to select 1
of 8 possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[2:0]
are don’t care during device selection. The device address present on the RDADD bus will be selected
on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout
bus, read from the previously selected Queue on this RCLK edge). Please refer to Table 2 for details
on RDADD bus.
The REN input enables read operations from a selected queue based on a rising edge of RCLK. A queue
to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless of the state
of REN. Data from a newly selected queue will be available on the Qout output bus on the second RCLK
cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not required
to cycle the PAEn/PRn bus (in polled mode) or to select the device , (in direct mode).
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI
input of the master device (or single device), should be controlled by the user.
10
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES