IDT72V51246L7-5BB IDT, Integrated Device Technology Inc, IDT72V51246L7-5BB Datasheet - Page 11

• Manufacturer Part Number: IDT72V51246L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51246L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51246L7-5BB

PIN DESCRIPTIONS (CONTINUED)
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
SENO
SI
SO
TCK
TDI
TDO
TMS
TRST
WADEN
Symbol
WCLK
(2)
(2)
(2)
(2)
(2)
Write Clock
Serial Output Enable
Serial In
Serial Out
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode Select
JTAG Reset
Write Address Enable
Name
I/O TYPE
OUTPUT has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO
OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the
OUTPUT operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
LVTTL
LVTTL
INPUT
LVTTL
LVTTL
INPUT
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
LVTTL
This output is used to indicate that serial programming or default programming of the multi-queue device
will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also
go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programming of the devices will be used, the SENO output
should be connected to the SENI input of the next device in the chain. When serial programming of the
first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
During serial programming this pin is loaded with the serial data that will configure the multi-queue
devices. Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In
expansion mode the serial data input is loaded into the first device in a chain. When that device is loaded
and its SENO has gone LOW, the data present on SI will be directly output to the SO output. The SO pin
of the first device connects to the SI pin of the second and so on. The multi-queue device setup registers
are shift registers.
This output is used in expansion mode and allows serial data to be passed through devices in the chain
chain. The SO of the final device in a chain should not be connected.
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation,test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces TRST HIGH if left unconnected.
The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN
should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note,
that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the
part has been completed and SENO has gone LOW.
When enabled by WEN, the rising edge of WCLK writes data into the selected queue via the input bus,
Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while
WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the device
to be placed on the PAFn bus during direct flag operation. During polled flag operation the PAFn bus is
cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and FF
outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based on
WCLK. The WCLK must be continuous and free-running.
11
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES