FAN5236QSCX Fairchild Semiconductor, FAN5236QSCX Datasheet - Page 13

• Manufacturer Part Number: FAN5236QSCX
• Description: IC CTRLR DDR/PWM DUAL HE 28QSOP
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5236QSCX

• Applications: Controller, Mobile-Friendly DDR
• Voltage - Input: 5 ~ 24 V
• Number Of Outputs: 2
• Voltage - Output: 0.9 ~ 5 V
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Operating Temperature Range: - 10 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FAN5236QSCXTR; FAN5236QSCX_NL; FAN5236QSCX_NLTR; FAN5236QSCX_NLTR

© 2002 Fairchild Semiconductor Corporation
FAN5236 • Rev. 1.3.2
More accurate sensing can be achieved by using a
resistor (R1) instead of the R
in Figure 13. This approach causes higher losses, but
yields greater accuracy in both V
low value resistor (e.g. 10mΩ).
Current limit (I
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. In
addition, since I
multiply I
25%). For example, in Figure 6, the target for I
I
Duty Cycle Clamp
During severe load increase, the error amplifier output
can go to its upper limit, pushing a duty cycle to almost
100% for significant amount of time. This could cause a
large increase of the inductor current and lead to a long
recovery from a transient, over-current condition, or
even to a failure at especially high input voltages. To
prevent this, the output of the error amplifier is clamped
to a fixed value after two clock cycles if severe output
voltage excursion is detected, limiting the maximum
duty cycle to:
This is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle
clamp is disabled and the maximum duty cycle is 87%.
Gate Driver Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive
signals, providing necessary amplification, level shifting,
and shoot-through protection. It also has functions that
optimize the IC performance over a wide range of
operating conditions. Since MOSFET switching time
can vary dramatically from type to type and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than
approximately 1V. Similarly, the upper MOSFET is not
turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1V.
This allows a wide variety of upper and lower MOSFETs
to be used without a concern for simultaneous
conduction or shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to function properly. Any
delay along that path subtracts from the delay
generated by the adaptive dead-time circuit and shoot-
through may occur.
DC
LIMIT
MAX
> 1.2 x 1.25 x 1.6 x 6A
=
V
V
OUT
LOAD(MAX)
IN
+
⎛
⎜
⎜
⎝
V
LIMIT
2
IN
4 .
LIMIT
⎞
⎟
⎟
⎠
) should be set high enough to allow
by the inductor ripple current (e.g.
is a peak current cut-off value,
≈
DS(ON)
14.5A
DROOP
of the FET, as shown
and I
LIMIT
LIMIT
. R1 is a
:
(6)
(7)
13
Frequency Loop Compensation
Due to the implemented current-mode control, the
modulator has a single-pole response with -1 slope at
frequency determined by load:
where R
For this type of modulator, a Type-2 compensation
circuit is usually sufficient. To reduce the number of
external components and simplify the design, the PWM
controller has an internally compensated error amplifier.
Figure 14 shows a Type-2 amplifier, its response, and
the responses of a current-mode modulator and the
converter. The Type-2 amplifier, in addition to the pole
at the origin, has a zero-pole pair that causes a flat gain
region at frequencies between the zero and the pole.
This region is also associated with phase “bump” or
reduced phase shift. The amount of phase-shift
reduction depends on the width of the region of flat gain
and has a maximum value of 90°. To further simplify the
converter compensation, the modulator gain is kept
independent of the input voltage variation by providing
feedforward of V
The zero frequency, the amplifier high-frequency gain,
and the modulator gain are chosen to satisfy most
typical applications. The crossover frequency appears
at the point where the modulator attenuation equals the
amplifier high-frequency gain. The system designer
must specify the output filter capacitors to position the
load main pole somewhere within a decade lower than
the amplifier zero frequency. With this type of
compensation, plenty of phase margin is achieved due
to zero-pole pair phase “boost.”
f
f
f
18
14
PO
Z
P
0
=
=
modul ator
=
2
2ππ
2
π
π
R
O
1
1
R
2
2
V
1
is load resistance; C
C
O
C
IN
f
C
1
2
P0
Figure 14.
O
=
=
6
600kHz
IN
R1
kHz
REF
to the oscillator ramp.
R2
f
Compensation
Z
C2
C1
O
is load capacitance.
EA Out
f
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P
(10)
(9)
(8)