NCP5378MNR2G ON Semiconductor, NCP5378MNR2G Datasheet - Page 8

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NCP5378MNR2G

Manufacturer Part Number
NCP5378MNR2G
Description
IC CTLR 1PH SYNC BUCK 32QFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NCP5378MNR2G

Applications
Controller, Power Supplies for Next-Generation Intel Processors
Voltage - Input
4.3 ~ 7 V
Number Of Outputs
1
Voltage - Output
0.5 ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-TFQFN Exposed Pad
Output Voltage
0.075 V to 3 V
Output Current
2 mA
Input Voltage
- 0.3 V to + 3 V
Operating Temperature Range
0 C to + 70 C
Mounting Style
SMD/SMT
Isolated/non-isolated
Non Isolated
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ELECTRICAL CHARACTERISTICS
0°C < T
3. Guaranteed by design.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
DAC OUTPUT
VID INPUTS
DIGITAL DAC SLEW RATE LIMITER
INPUT SUPPLY CURRENT
V
BOOST PIN UVLO
STARTUP HIGH SIDE SHORT TRIP (Active only during 1
HIGH SIDE DRIVER
LOW SIDE DRIVER
Output Source Current
Output Sink Current
Threshold
VR11 Mode Leakage
Delay before Latching VID Change
(VID Deskewing) (Note 3)
Slew Rate Limit
Soft−Start Slew Rate
V
V
V
V
V
BOOST UVLO Start Threshold (Note 3)
BOOST UVLO Stop Threshold (Note 3)
BOOST UVLO Hysteresis (Note 3)
V
Startup
R
R
Tr
Tf
Tpdh
R
R
Tr
Tf
Tpdh
V
(Note 3)
CCP
CC
CCP
CCP
CCP
CCP
swx
NCDT
H_TG
H_TG
H_BG
L_BG
DRVH
DRVH
DRVL
DRVL
Quiescent Current
DRVH
DRVL
Output Overvoltage Trip Threshold at
SUPPLY VOLTAGE
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
POR
A
Output Resistance, Sourcing
Output Resistance, Sinking
Output Resistance, Sinking
Output Resistance, Sourcing
Negative Current Detector Threshold
Transition Time
Transition Time
Transition Time
Transition Time
< 70°C; 0°C < T
Propagation Delay (Note 4)
Propagation Delay (Note 4)
Parameter
J
< 125°C; 4.75 < V
CC
< 5.25 V; All DAC Codes; C
V
V
Measured from the edge of the 1
change
EN Low, No PWM
Voltage at which the Driver OVP
becomes active
Power Startup time, V
V
V
C
C
Driving High, C
V
SW = GND
SW = V
C
C
Driving High, C
V
out
out
BST
BST
CCP
CCP
LOAD
LOAD
LOAD
LOAD
http://onsemi.com
= 1.6 V
= 0.3 V
− V
− V
= 12 V
= 12 V
st
= 3 nF, V
= 3 nF, V
= 3 nF
= 3 nF
CC
power on)
SW
SW
Test Conditions
= 12 V
= 12 V
8
LOAD
LOAD
BST
BST
− V
− V
= 3.3 nF,
= 3.3 nF,
VCC
CC
SW
SW
> 9 V
= 0.1 mF unless otherwise noted.
= 12 V
= 12 V
st
VID
−100
12.5
3.15
Min
450
200
5.0
8.2
7.2
1.0
3.0
3.0
1.7
10
50
0
0.84
−4.0
Typ
600
200
9.0
8.0
3.2
1.8
1.0
1.6
1.0
25
20
15
20
20
20
Max
4.15
3.85
2.03
770
100
300
5.0
9.5
8.5
16
16
30
mV/ms
mV/ms
Unit
mA
mA
mV
mA
mV
mV
nA
ns
ns
ns
ns
ns
ns
ns
W
W
W
V
V
V
V
V
V

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