NCP5378MNR2G ON Semiconductor, NCP5378MNR2G Datasheet - Page 11

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NCP5378MNR2G

Manufacturer Part Number
NCP5378MNR2G
Description
IC CTLR 1PH SYNC BUCK 32QFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NCP5378MNR2G

Applications
Controller, Power Supplies for Next-Generation Intel Processors
Voltage - Input
4.3 ~ 7 V
Number Of Outputs
1
Voltage - Output
0.5 ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-TFQFN Exposed Pad
Output Voltage
0.075 V to 3 V
Output Current
2 mA
Input Voltage
- 0.3 V to + 3 V
Operating Temperature Range
0 C to + 70 C
Mounting Style
SMD/SMT
Isolated/non-isolated
Non Isolated
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
and should not jump up when the fault cleared.
Differential Current Feedback Amplifier
current of each phase.
corresponding phase. A voltage is generated across a current
sense element such as an inductor or sense resistor. The
sense voltage will be very low. The sense element will
normally be between 0.5 mW and 1.5 mW. It is possible to
sense both negative and positive going current. It is further
possible that the differential sense signal is below 0 V. The
output of these amplifiers shall not invert if the common
mode range is exceeded.
output of the amplifier is used to control 3 functions. First,
the output controls the adaptive voltage positioning, where
the output voltage is actively controlled according to the
output current. Second, the output signal is fed to the current
limit circuit. Finally, the phase current is connected to the
PWM comparator. The offset voltage difference from
amplifier to amplifier and the error in bias current from
amplifier to amplifier need to be minimized. The offset and
bias current design needs to be able to eliminate differences
from amplifier to amplifier.
Switching Frequency in RPM Mode
frequency is controlled by the ripple voltage on the COMP
pin. Each time the COMP pin voltage exceeds the RPM pin
voltage threshold level determined by the VID voltage and
the external resistor connected between RPM and ground, an
internal ramp signal is started and TG is driven high. The
slew rate of the internal ramp is programmed by the current
entering the ROSC pin. When the internal ramp signal
intercepts the COMP voltage, the TG pin is reset low. In
continuous current mode, the switching frequency of RPM
operation is almost constant. While in discontinuous current
conduction mode, the switching frequency is reduced as a
function of the load current.
Soft Start
steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table.
reads the DAC setting, then ramps to the final DAC setting.
Digital Slew Rate Limiter / Soft Start Block
implemented with a digital up/down counter controlled by
an oscillator that can be synchronized to VID line changes.
During soft start the DAC will ramp at the softstart rate, after
soft start is complete the ramp rate will follow the Intel rate
depending on the mode. In normal operation the design must
keep up with the Intel spec of 1 DAC step every 1.25 ms.
The comp pin will be pulled to ground in a fault condition
A differential amplifier are provided to sense the output
The current sense amplifier senses the current through its
The gain of this amplifier is fixed and is noninverting. The
When the NCP5378 operates in RPM mode, its switching
Soft start is implemented internally. A digital counter
The VR11 mode ramps DAC to 1.1 V, pauses for 500 ms,
The slew rate limiter and the soft−start block are to be
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11
possible (less than 20 mV out the DAC Buffer) in order to avoid
the output voltage jumping up at the beginning of the ramp.
deliver less than 20 mV. The digital DAC offset should be
introduced prior to the digital compare.
Protection Features
Undervoltage Lockouts
the controller and driver voltage rail. During power up the
input voltage to the controller is monitored. The PWM
outputs and the soft start circuit are disabled until the input
voltage exceeds the threshold voltage of the comparator.
Hysteresis is incorporated within the comparator.
threshold is exceeded. If V
threshold, the output gate will be forced low unit input
voltage V
Overcurrent Latch
the IC. The oscillator pin provides the reference voltage for
this pin. A resistor divider from this pin generates the
reference voltage. The latch is set when the current
information exceeds the programmed voltage. To recover
the part must be reset by the EN pin or by cycling V
EN is removed and reapplied.
UVLO Monitor
DAC voltage the UVLO comparator will trip sending the
VR_RDY signal low.
Overvoltage Protection
differential amplifier. During normal operation, if the output
voltage exceeds the DAC voltage by 180 mV (OR 350 mV
if OFS is active), the VR_RDY flag goes low, the high side
gate drivers are all brought low, and the low side gate drivers
are all brought high until the voltage falls below the OVP
threshold. If the over voltage trip 8 times the output voltage
will shut down. The OVP will not shut down the controller
if it occurs during soft−start. This is to allow the controller
to pull the output down to the DAC voltage and start up into
a pre−charged output.
V
the CPU during startup. When V
gate driver will monitor the switching node SW pin. If SWN
pin higher than 1.9 V, the bottom gate will be forced to high
for discharge of the output capacitor. This works best if the
5 V standby is diode OR’ed into V
CCP
The DAC must be implemented down as close to zero as
Preferably when DAC = 0 the buffer to the RS amp should
An undervoltage circuit senses the input V
The PWM signals will control the gate status when V
A programmable overcurrent latch is incorporated within
The outputs will remain disabled until the V
If the output voltage falls greater than 300 mV below the
The output voltage is monitored at the input of the
The V
Power ON Reset OVP
CCP
CC
power on reset OVP feature is used to protect
rises above the startup threshold.
CC
CCP
decreases below the stop
CCP
is higher than 3.2 V, the
with the 12 V rail. The
CC
CC
and V
voltage or
CCP
CC
.
CC
of

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