NCP5378MNR2G ON Semiconductor, NCP5378MNR2G Datasheet - Page 12

• Manufacturer Part Number: NCP5378MNR2G
• Description: IC CTLR 1PH SYNC BUCK 32QFN
• Manufacturer: ON Semiconductor

Specifications of NCP5378MNR2G

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 4.3 ~ 7 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Output Voltage: 0.075 V to 3 V
• Output Current: 2 mA
• Input Voltage: - 0.3 V to + 3 V
• Operating Temperature Range: 0 C to + 70 C
• Mounting Style: SMD/SMT
• Isolated/non-isolated: Non Isolated
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

fault mode will be latched unless V
UVLO threshold.
Power Saving Mode
mode. The 12VMON input will be used for two purposes:
feedforward input supply information for RPM mode and
secondary power input voltage UVLO.
Adaptive Non−overlap
through damage to the power MOSFETs. When the PWM
signal pull high, BG will go low after a propagation delay,
the controller monitors the switching node (SWN) pin
voltage and the gate voltage of the MOSFET to know the
status of the MOSFET. When the low side MOSFET status
is off an internal timer will delay turn on of the high–side
MOSFET. When the PWM pull low, gate TG will go low
after the propagation delay (tpdlDRVH). The time to turn off
the high side MOSFET is depending on the total gate charge
of the high−side MOSFET. A timer will be triggered once
the high side MOSFET is turn off to delay the turn on the
low−side MOSFET.
Externally Programmable Offset
for generating an offset voltage across the resistor, R
between FB and V
an external resistor and precision internal voltage
references. For positive offset connect a resistor to GND.
The device maintains a RPM operation in power saving
The non−overlap dead time control is used to avoid shoot
The OFS pin provides a means to program a DC current
DIFF
. The offset current is generated via
CCP
is reduced below the
http://onsemi.com
FB
12
For negative offset connect a resistor to V
no-load offset on NCP5378 is −19 mV.
For Negative Offset connect R
For Positive Offset connect R
a nominal of -19mV)
Layout Guidlines
converter. The strap capacitor and Vin capacitor are most
critical items, it should be placed as close as to the controller
IC. Another item is using a GND plane. Ground plane can
provide a good return path for gate drives for reducing the
ground noise. Therefore GND pin should be directly
connected to the ground plane and close to the low−side
MOSFET source pin. Also, the gate drive trace should be
considered. The gate drives has a high di/dt when switching,
therefore a minimized gate drives trace can reduce the di/dv,
raise and fall time for reduce the switching loss.
To set the no−load offset please use the equations below:
For example to get 0 mV no-load offset; (since the part has
Layout is very important thing for design a DC−DC
R
OFS
R
R
OFS
OFS
+
V
+
+
CC
0.3
0.3
V
V
OFS
* 2.0 @ R
19 mV
OFS
OFFSET
OFFSET
to GND
R
R
to V
FB
FB
CC
FB
CC
. The nominal