TLE6230GP Infineon Technologies, TLE6230GP Datasheet - Page 6

• Manufacturer Part Number: TLE6230GP
• Description: IC SW SMART OCTAL LOWSIDE PDSO36
• Manufacturer: Infineon Technologies
• Type: Low Sider

Specifications of TLE6230GP

• Input Type: SPI
• Number Of Outputs: 8
• On-state Resistance: 800 mOhm
• Current - Peak Output: 1.5A
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-36
• Switch Type: Low Side
• Power Switch Family: TLE6230
• Input Voltage: -0.3 to 7V
• Power Switch On Resistance: 800mOhm
• Output Current: 1A
• Mounting: Surface Mount
• Supply Current: 1mA
• Package Type: DSO
• Operating Temperature (min): -40C
• Operating Temperature (max): 150C
• Operating Temperature Classification: Automotive
• Pin Count: 38
• Power Dissipation: 3300W
• Packages: PG-DSO-36
• Thermal Class: Heatslug down
• Id Nom: 8 x 0.5 A
• Channels: 8.0
• Comment: relay driver and general purpose
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Lead Free Status / Rohs Status: Compliant
• Other names: SP000012169; SP000691114; TLE6230GP; TLE6230GPNT; TLE6230GPT; TLE6230GPT; TLE6230GPTR

Electrical Characteristics cont.
Parameter and Conditions
V
(unless otherwise specified)
5. Diagnostic Functions
Open Load Detection Voltage
Output Pull Down Current
Fault Delay Time
Short to Ground Detection Voltage
Short to Ground Detection Current
Current Limitation; Overload Threshold Current
Overtemperature Shutdown Threshold
Hysteresis
6. SPI-Timing
Serial Clock Frequency (depending on SO load)
Serial Clock Period (1/fclk)
Serial Clock High Time
Serial Clock Low Time
Enable Lead Time (falling edge of
Enable Lag Time (falling edge of CLK to rising edge of
Data Setup Time (required time SI to falling of CLK)
Data Hold Time (falling edge of CLK to SI)
Disable Time @ C
Transfer Delay Time
(
Data Valid Time
6
7
V2.3
CS
This parameter will not be tested but guaranteed by design
This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay
time has to be extended to the maximum fault delay time t
S
= 4.5 to 5.5 V ; T
high time between two accesses)
6
L
= 50 pF
j
7
= - 40 °C to + 150 °C ; Reset = H
6
CS
to rising edge of
6
C
C
C
L
L
L
Page
= 50 pF
= 100 pF
= 220 pF
d(fault)max
CS
CLK
6
6
6
6
)
) t
Symbol
V
I
t
V
I
I
T
T
f
t
t
t
t
t
t
t
t
t
PD(OL)
d(fault)
SHG
D(lim) 1...8
SCK
p(SCK)
SCKH
SCKL
lead
lag
SU
H
DIS
dt
valid
= 200µs.
th(sd)
hys
DS(OL)
DS(SHG)
Data Sheet TLE 6230 GP
Values
V
V
50
50
-50
1
170
--
DC
200
50
50
250
250
20
20
--
200
--
--
--
S
min
S
–3.3 V
-2.5 V
--
--
--
--
--
---
--
--
--
--
150
90
100
-100
1.5
--
10
110
120
S
S
typ
-2.9 V
-2 V
150
200
-150
2
200
--
5
--
--
--
--
--
--
--
150
--
160
170
200
S
S
18. Nov. 2009
max
-1.3
-2.5
Unit
V
µA
µs
V
µA
A
°C
K
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns